Datasheet > P4C1256-55DM

P4C1256-55DM

更新时间： 2024-09-24 06:01:23

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
8页	89K
描述
HIGH SPEED 32K x 8 STATIC CMOS RAM

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中文翻译

获取价格

数据手册

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P4C1256-55DM 数据手册

P4C1256

HIGH SPEED 32K x 8

STATIC CMOS RAM

FEATURES

Three-State Outputs

High Speed (Equal Access and Cycle Times)

— 12/15/20/25/35 ns (Commercial)

— 15/20/25/35/45 ns (Industrial)

— 20/25/35/45/55/70 ns (Military)

Low Power

— 880 mW Active (Commercial)

Single 5V±10% Power Supply

Easy Memory Expansion Using CE and OE

Inputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t_OE

Automatic Power Down

Packages

—28-Pin 300 mil DIP and SOJ

—28-Pin 600 mil Ceramic DIP

—28-Pin LCC(350 mil x 550 mil)

—32-Pin LCC (450 mil x 550 mil)

Common Data I/O

DESCRIPTION

The P4C1256 is a 262,144-bit high-speed CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

The P4C1256 device provides asynchronous operation with

matching access and cycle times. Memory locations are

specified on address pins A₀to A₁₄. Reading is accom-

plished by device selection (CE and output enabling (OE)

while write enable (WE) remains HIGH. By presenting the

address under these conditions, the data in the addressed

memory location is presented on the data input/output pins.

The input/output pins stay in the HIGH Z state when either

CE or OE is HIGH or WE is LOW.

Access times as fast as 12 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The

P4C1256 is a member of a family of PACE RAM™ prod-

ucts offering fast access times.

Package options for the P4C1256 include 28-pin 300 mil

DIP and SOJ packages. For military temperature range,

Ceramic DIP and LCC packages are available.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

VCC

262,144-BIT

MEMORY

ARRAY

(8)

31 30

A14

A13

A12

I/O

INPUT

DATA

CONTROL

COLUMN I/O

I/O

I/0

I/01

I/O

I/02

14 15 16 17 18 19 20

COLUMN

SELECT

I/03

GND

• • • • • •

DIP (P5, C5, D5-1), SOJ (J5)

TOP VIEW

1519B

32 LCC (L6)

TOP VIEW

(7)

See Selection Guide page for 28-pin LCC

Means Quality, Service and Speed

1Q97

117

12 3 4 5 6 7 8

中文翻译

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与P4C1256-55DM相关器件

型号	品牌	获取价格	描述	数据表
P4C1256-55DMB	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-55DMBLF	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, DIP-28
P4C1256-55DWC	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-55DWCLF	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, DIP-28
P4C1256-55DWI	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-55DWILF	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, DIP-28
P4C1256-55DWM	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-55DWMB	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
P4C1256-55DWMBLF	PYRAMID	获取价格	暂无描述
P4C1256-55DWMLF	PYRAMID	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, CDIP28, 0.600 INCH, ROHS COMPLIANT, CERAMIC, DIP-28

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