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P1757M-20PGM

更新时间： 2024-11-08 03:03:19

品牌	Logo	应用领域
PYRAMID		/
页数	文件大小	规格书
34页	651K
描述
COMPLETE EMBEDDED CPU SUBSYSTEM

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P1757M-20PGM 数据手册

PACE1757M/ME

COMPLETE EMBEDDED CPU SUBSYSTEM

FEATURES

Programmable memory and I/O data wait

state generation permits up to four different

memory speeds in the same system.

Implements complete MIL-STD-1750A ISA including

optional MMU, MFSR, and BPU functions.

Two throughput options:

P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz

P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz

Programmable address wait states.

Sixteen levels of interrupts are provided per

MIL-STD-1750A. Interrupts can be either

edge- or level-sensitive.

All MIL-STD-1750A data formats and address

types implemented.

Fault detection and handling

P1757ME includes additional matrix and vector

instructions to enhance throughput in

navigation, DSP transcendental and other

complex alorithms.

Programmable detection of unimplemented

memory or illegal I/O addresses.

Full implementation of MIL-STD-1750A fault

Error detection and correction and parity bit

provided.

External address error detection.

Testability and diagnostics.

Separate high drive external address & data

busses.

First falling address and data registers.

10MHz data rate at 40MHz CPU clock

System support functions included:

Built in test - runs automatically at power on

and after each reset. All hardware blocks

and external busses examined. Hardware

pass/fail for catastrophic failures. Status

Arbitrator for use in tightly coupled

multiprocessor design. Bus control provided

to aid in implementation of multi-processor

systems.

Console operating mode which allows

operator to examine and change contents of

registers within the CPU, any system

memory location, or the I/O subsystems.

MIL-STD-1750A timers A & B, programmable

watch dog timer and programmable bus time-

out function.

Single 144-pin Quad straight lead or Gullwing

1.5 square inches of board surface.

Start up ROM support per MIL-STD-1750A.

DMA support for logical and physical memory

addresses.

Operating temperature range -55 to +125°C;

single 5V ± 10% V power supply; power

dissipation < 1.9W (worst case at 40 MHz).

GENERAL DESCRIPTION

The PACE 1757M uses the application-proven PACE

1750A microprocessor, the PACE 1753, and the PACE

1754. The PACE1757ME uses the enhanced PACE

1750AEmicroprocessor,whichhasadditionalinstructions

thatprovidehighthroughputfortranscendentalfunctions,

navigational algorithms, and DSP functions. The PACE

1750AE is an architectural enhancement of the PACE

1750A.

All functions required for a complete MIL-STD-1750A

embedded CPU subsystem are in this single VLSI

microcircuit occupying 1.5 square inches of board space

with less than 1.9 watts of power dissipation at 40 MHz.

Pyramid'sP1757M/MEisacomplete,singlepackage,3.6

MIPS subsystem solution to embedded processor

requirements.

Do c um e nt # MICRO-10 REV B

Re vise d Aug ust 2005

12 3 4 5 6 7...34

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与P1757M-20PGM相关器件

型号	品牌	获取价格	描述	数据表
P1757M-20PGMB	PYRAMID	获取价格	Microprocessor, 20MHz, CMOS, CPGA144, PGA-144
P1757M20QGM	ETC	获取价格	Microprocessor
P1757M20QGMB	PYRAMID	获取价格	Microprocessor
P1757M20QLM	ETC	获取价格	Microprocessor
P1757M-20QLM	PYRAMID	获取价格	COMPLETE EMBEDDED CPU SUBSYSTEM
P1757M20QLMB	ETC	获取价格	Microprocessor
P1757M-20QLMB	PYRAMID	获取价格	Microprocessor, 20MHz, CMOS, QFP-144
P1757M-30PGM	PYRAMID	获取价格	COMPLETE EMBEDDED CPU SUBSYSTEM
P1757M-30PGMB	PYRAMID	获取价格	Microprocessor, 30MHz, CMOS, CPGA144, PGA-144
P1757M30QGM	PYRAMID	获取价格	Microprocessor

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