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P1753-20CMB

更新时间： 2024-11-08 04:11:31

品牌	Logo	应用领域
PYRAMID		/
页数	文件大小	规格书
21页	187K
描述
SINGLE CHIP, 40MHz CMOS MMU/COMBO

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技术参数
数据手册

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P1753-20CMB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5
其他特性：	6 EDAC BITS FOR DETECTION OF DOUBLE ERROR AND CORRECTION OF SINGLE ERROR ON DATA BUS	地址总线宽度：	16
最长地址转换时间：	25 ns	总线兼容性：	PACE1750
最大时钟频率：	20 MHz	外部数据总线宽度：	16
JESD-30 代码：	R-XDIP-T64	长度：	42.2402 mm
低功率模式：	NO	可寻址页面数量：	256
端子数量：	64	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15.24 mm
uPs/uCs/外围集成电路类型：	MEMORY MANAGEMENT UNIT	Base Number Matches：	1

P1753-20CMB 数据手册

PACE1753

SINGLE CHIP, 40MHz

CMOS MMU/COMBO

FEATURES

— Illegal address error detection—

programmable

— Multi-Master arbitration

Implements the MIL-STD-1750A Instruction Set

Architecture for Memory Management and

Protection of up to 1 Megaword. All mapping

memory (10,240 bits) for both the MMU and

BPU functions are included on the chip.

8-bit extended address latches and drivers on

chip

Designed to interface memory to the

PACE1750A/AE 16-bit, 40 MHz processor.

Systems can be designed where no WAIT

states are required up to 40 MHz clock rates

when using these PACE products.

Information bus and EDAC transceivers on chip

20, 30 and 40 MHz operation over the Military

Temperature Range

Single 5V ± 10% Power Supply

System performance and device count are

optimized when used with the PACE1754

Processor Interface Circuit (PIC).

Power Dissipation over Military Temperature

Range (P Outputs Open)

< 0.20 watts at 20 MHz

< 0.30 watts at 30 MHz

< 0.40 watts at 40 MHz

Provides the following additional functions:

— EDAC, Error Detection and Correction—or

parity generation and detection

Available in:

— Correct data register—for diagnostics

— First memory failing address register

— 64-Pin DIP or Gull Wing (50 Mil Pin centers)

— 68-Pin Pin Grid Array (PGA) (100 Mil centers)

— 68-Lead Quad Pack (Leaded Chip Carrier)

MEMORY MANAGEMENT UNIT AND

BLOCK PROTECT UNIT “COMBO” —

FUNCTIONAL DESCRIPTION

The PACE1753 (COMBO) is a support chip for the

PACE1750A/AE microprocessor family. It provides the

following supporting functions to the system:

1. Memory management and access protection for up

to 1M words.

Physical memory write protection for up to 1M words

memory in pages of 1K words each. Separate

protection is provided for the CPU and for DMA in

systems which include DMA.

3. Detection of illegal l/O accesses (as defined by MIL-

STD-1750A) or access to an unimplemented block

of memory. In each case an error flag is generated

to the processor.

Detection of double errors on the data bus and

correctionofsingleerrors. Anerrorsignalisgenerated

to the processor when a multiple error is detected.

5. RDYA generation. Up to three wait states can be

insertedintheaddressphaseofthebusbygenerating

a not-ready, RDYA low signal. The number of wait

states required can be programmed in an internal

6. Bus arbitration for up to 4 masters. Arbitration is

done on a fixed priority basis (i.e. by interconnection

of hardware). (In 68 pin package only).

Do c um e nt # MICRO-4 REV D

Re vise d No ve m b e r 2005

12 3 4 5 6 7...21

中文翻译

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与P1753-20CMB相关器件

型号	品牌	获取价格	描述	数据表
P1753-20GC	PYRAMID	获取价格	Memory Management Unit, 16-Bit, 256 Pages, CMOS, CDSO64
P1753-20GMB	PYRAMID	获取价格	SINGLE CHIP, 40MHz CMOS MMU/COMBO
P1753-20PGC	PYRAMID	获取价格	Memory Management Unit, 16-Bit, 256 Pages, CMOS, CPGA68
P1753-20PGMB	PYRAMID	获取价格	SINGLE CHIP, 40MHz CMOS MMU/COMBO
P1753-20QGMB	PYRAMID	获取价格	SINGLE CHIP, 40MHz CMOS MMU/COMBO
P1753-20QLC	PYRAMID	获取价格	Memory Management Unit, 16-Bit, 256 Pages, CMOS, CQFP68
P1753-20QLMB	PYRAMID	获取价格	SINGLE CHIP, 40MHz CMOS MMU/COMBO
P1753-30CC	PYRAMID	获取价格	Memory Management Unit, 16-Bit, 256 Pages, CMOS, CDIP64
P1753-30CMB	PYRAMID	获取价格	SINGLE CHIP, 40MHz CMOS MMU/COMBO
P1753-30GC	PYRAMID	获取价格	Memory Management Unit, 16-Bit, 256 Pages, CMOS, CDSO64

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