P1750A/SOS
SINGLE CHIP, 20MHz to 30MHz,
CMOS/SOS SPACE PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
Built-In Self Test
24 User Accessible Registers
Single 5V ± 10% Power Supply
CMOS/SOS Processor with 32 and 48-Bit
Floating Point Arithmetic
TTL Signal Level compatible Inputs and
Outputs
Integer DAIS Mix Performance
3.0 MIPS at 30 MHz
Multiprocessor and Co-processor capability
Available with Class S type manufacturing,
screening, and testing
Built-In Function (BIF) for User Defined
Instructions
SOS Insulated substrate technology provides
absolute latch up immunity and excellent SEU
tolerance
Two programmable Timers
SOS devices are fully interchangeable with
application-proven CMOS P1750A Processors;
SMD 5962-87665
Total Dose ≥ 100 Krads (Si)
20, 25, and 30 MHz operation over the Military
Temperature Range
Available in:
- 68-Lead Quad Pack (Leaded Chip Carrier) with
Optional Gull Wing
Extensive Error and Fault Management and
Interrupt Capability
GENERAL DESCRIPTION
The chip includes 16 general purpose registers, 8 other
user-accessible registers, and an array of real time
application support resources, such as 2 programmable
timers, a complete interrupt controller supporting 16
levels of prioritized internal and external interrupts, and a
faults and exceptions handler controlling internally and
externally generated faults.
ThePACE1750Aisageneralpurpose,application-proven,
single chip, 16-bit CMOS microprocessor designed for
high performance floating point and integer arithmetic,
with extensive real time environment support. It offers a
variety of data types, including bits, bytes, 16-bit and 32-
bit integers, and 32-bit and 48-bit floating point numbers.
Itprovides13addressingmodes,includingdirect,indirect,
indexed, based, based indexed and immediate long and
short,anditcanaccess2MWordsofsegmentedmemory
space (64 KWords segments without use of a MIL-STD-
1750A MMU).
TheP1750Ausesasinglemultiplexed16-bitparallelbus.
Status signals are provided to determine whether the
processor is in the memory or I/O bus cycle, reading and
writing,andwhetherthebuscycleisfordataorinstructions.
The PACE1750A offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer,floatingpoint,integer-to-floatingpointandfloating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions
such as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, supports executive and user modes, and
providesanescapemechanismwhichallowsuser-defined
instructions using a coprocessor. The instruction set is
fully compliant with MIL-STD-1750A.
The basic bus cycle is 4 clocks long. The P1750A will
extend the cycle by insertion of wait states in the address
and data phases (in response to RDYA and RDYD
signals, repectively) and will hold the machine in HI-Z if
this CPU has not acquired the bus. A typical non-bus
cycle is three clocks long. However, variable length
cyclesareusedforsuchrepetitiveoperationsasmultiply,
divide, scale and normalize, reducing significantly the
numberofCPUCLOCKSperoperationstepandresulting
in very fast integer and floating point execution times.
Do c um e nt # MICRO-6 REV B
Re vise d Aug ust 2005