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P1750AE-30QLMB PDF预览

P1750AE-30QLMB

更新时间： 2024-11-08 02:51:23
品牌 Logo 应用领域
PYRAMID 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
25页 230K
描述
SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR

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中文翻译

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P1750AE-30QLMB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：QFF,针数：68
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.34
Is Samacsys：N其他特性：2.7 MIPS DAIS MIX; TWO PROGRAMMABLE TIMERS; FAST POLYNOMIAL EXPANSION ALGORITHM
地址总线宽度：16位大小：16
边界扫描：NO最大时钟频率：30 MHz
外部数据总线宽度：16格式：FLOATING POINT
集成缓存：NOJESD-30 代码：S-XQFP-F68
长度：24.26 mm低功率模式：NO
端子数量：68最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：UNSPECIFIED
封装代码：QFF封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2.95 mm
速度：30 MHz最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24.26 mm
uPs/uCs/外围集成电路类型：MICROPROCESSORBase Number Matches：1

P1750AE-30QLMB 数据手册

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PACE1750AE  
SINGLE CHIP, 20MHz to 40MHz, ENHANCED  
CMOS 16-BIT PROCESSOR  
FEATURES  
Implements the MIL-STD-1750A Instruction Set  
Architecture  
Single Chip PACE Technology CMOS 16-Bit  
Processor with 32 and 48-Bit Floating Point  
Arithmetic  
Matrix Computations up to 64K  
– Fast Polynomial expansion algorithms  
– Fast context switching with Instruction to  
block move up to 16 new mapping memory  
page registers  
TM  
Form-Fit-Functionally Compatible with the  
P1750A  
20, 30, and 40 MHz Operation over the Military  
Temperature Range  
DAIS Instruction Mix Execution Performance  
Including Floating Point Arithmetic  
1.8 MIPS at 20 MHz  
2.7 MIPS at 30 MHz  
3.6 MIPS at 40 MHz  
Conventional Integer Processing Mix  
Performance  
Extensive Error and Fault Management and  
Interrupt Capability  
26 User Accessible Registers  
Single 5V ± 10% Power Supply  
Power Dissipation over Military Temperature  
Range  
<0.5 watts at 20 & 30 MHz  
<1.0 watts at 40 MHz  
TTL Signal Level Compatible Inputs and  
Outputs  
Multiprocessor and Co-processor Capability  
Two programmable Timers  
Available in:  
5.0 MIPS at 40 MHz  
Power BIF Instructions Allow for High  
Throughput Implementations of Transcedental  
Functions, Navigational Algorithms and DSP  
Functions  
– Inner Dot Product Instruction for 3X3, 16 Bit  
Registers in 150ns (2 clocks per Multiply/  
Accumulate step) with 32 Bits Result  
– 64-Pin Top Brazed DIP  
– Multiply/Accumulate Instructions for 32 Bit  
Registers is 200ns at 40MHz (8 clocks), with  
48 Bit Result  
– 68-Pin Pin Grid Array (PGA)  
– 68-Lead Quad Pack (Leaded Chip Carrier)  
– Parameteric Memory Inner-Dot Products for  
GENERAL DESCRIPTION  
Thechipincludesanarrayofrealtimeapplicationsupport  
resources, such as 2 programmable timers, a complete  
interrupt controller supporting 16 levels of prioritized  
internalandexternalinterrupts,andafaultsandexceptions  
handler controlling internally and externally generated  
faults.  
The PACE1750AE is a general purpose, single chip, 16-  
bitCMOSmicroprocessordesignedforhighperformance  
floating point and integer arithmetic, with extensive real  
timeenvironmentsupport. Itoffersavarietyofdatatypes,  
includingbits, bytes, 16-bitand32-bitintegers, and32-bit  
and48-bitfloatingpointnumbers. Itprovides13addressing  
modes, including direct, indirect, indexed, based, based  
indexed and immediate long and short, and it can access  
2 MWords of segmented memory space (64 KWords  
segments).  
Themicroprocessorachievesveryhighthroughputof3.6  
MIPS for a standard real time integer/floating point  
instructionmixata40MHzclock. ItexecutesintegerAdd  
in 0.1 µs, integer Multiply in 0.1 µs, Floating Point Add in  
0.45 µs, and Floating Point Multiply in 0.225 µs, for  
register operands at a 40 MHz clock speed.  
The PACE1750AE offers a well-rounded instruction set  
with 130 instruction types, including a comprehensive  
integer,floatingpoint,integer-to-floatingpointandfloating  
point-to-integer set, a variety of stack manipulation  
instructions, high level language support instructions  
such as Compare Between Bounds and Loop Control  
Instructions. It also offers some unique instructions such  
as vectored l/O, supports executive and user modes, and  
providesanescapemechanismwhichallowsuser-defined  
instructions, using a coprocessor.  
ThePACE1750AEusesasinglemultiplexed16-bitparallel  
bus. Status signals are provided to determine whether  
the processor is in the memory or I/O bus cycle, reading  
and writing, and whether the bus cycle is for data or  
instructions.  
Do c um e nt # MICRO-2 REV G  
Re vise d Oc to b e r 2005  
1234567...25

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