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P1750A-30GMB PDF预览

P1750A-30GMB

更新时间： 2024-09-19 04:11:31
品牌 Logo 应用领域
PYRAMID /
页数 文件大小 规格书
24页 229K
描述
SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR

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中文翻译

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P1750A-30GMB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：64
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.51
其他特性：1.9 MIPS DAIS MIX; TWO PROGRAMMABLE TIMERS地址总线宽度：16
位大小：16边界扫描：NO
最大时钟频率：30 MHz外部数据总线宽度：16
格式：FLOATING POINT集成缓存：NO
JESD-30 代码：R-XDSO-G64长度：42.2402 mm
低功率模式：YES端子数量：64
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：UNSPECIFIED封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
筛选级别：MIL-STD-883 Class B座面最大高度：4.191 mm
速度：30 MHz最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14.98 mm
uPs/uCs/外围集成电路类型：MICROPROCESSORBase Number Matches：1

P1750A-30GMB 数据手册

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PACE1750A  
SINGLE CHIP, 15MHz to 40MHz,  
CMOS 16-BIT PROCESSOR  
FEATURES  
Implements the MIL-STD-1750A Instruction Set  
Architecture  
Single Chip PACE Technology CMOS 16-Bit  
Processor with 32 and 48-Bit Floating Point  
Arithmetic  
DAIS Instruction Mix Execution Performance  
Including Floating Point Arithmetic  
15, 20, 30, and 40 MHz Operation over the  
Military Temperature Range  
Extensive Error and Fault Management and  
Interrupt Capability  
24 User Accessible Registers  
Single 5V ± 10% Power Supply  
TM  
Power Dissipation over Military Temperature  
Range  
1.3 MIPS at 20 MHz  
1.9 MIPS at 30 MHz  
2.6 MIPS at 40 MHz  
< 0.30 watts at 20 MHz  
< 0.35 watts at 30 MHz  
< 0.40 watts at 40 MHz  
TTL Signal Level Compatible Inputs and  
Outputs  
Multiprocessor and Co-processor Capability  
Built-In Function (BIF) for User Defined  
Instructions  
Two programmable Timers  
Available in:  
– 64-Pin DIP or Gull Wing (50 Mil Pin Centers)  
– 68-Pin Pin Grid Array (PGA)  
– 68-Lead Quad Pack (Leaded Chip Carrier)  
Integer DAIS Mix Performance  
3.9 MIPS at 40 MHz  
Conventional Integer Processing Mix  
Performance  
5.0 MIPS at 40 MHz  
Instruction Execution at 40 MHz over the  
Military Temperature Range  
0.10 µsec Integer Add/Sub  
0.57 µsec Integer Multiply  
0.70 µsec Floating Point Add/Sub  
1.07 µsec Floating Point Multiply  
GENERAL DESCRIPTION  
levels of prioritized internal and external interrupts, and a  
faults and exceptions handler controlling internally and  
externally generated faults.  
The PACE1750A is a general purpose, single chip, 16-bit  
CMOS microprocessor designed for high performance  
floating point and integer arithmetic, with extensive real  
timeenvironmentsupport. Itoffersavarietyofdatatypes,  
includingbits, bytes, 16-bitand32-bitintegers, and32-bit  
and48-bitfloatingpointnumbers. Itprovides13addressing  
modes, including direct, indirect, indexed, based, based  
indexed and immediate long and short, and it can access  
2 MWords of segmented memory space (64 KWords  
segments).  
Themicroprocessorachievesveryhighthroughputof2.6  
MIPS for a standard real time integer/floating point  
instructionmixata40MHzclock. ItexecutesintegerAdd  
in 0.1 µs, integer Multiply in 0.575 µs, Floating Point Add  
in 0.7 µs, and Floating Point Multiply in 1.075 µs, for  
register operands at a 40 MHz clock speed.  
ThePACE1750Ausesasinglemultiplexed16-bitparallel  
bus. Status signals are provided to determine whether  
the processor is in the memory or I/O bus cycle, reading  
and writing, and whether the bus cycle is for data or  
instructions.  
The PACE1750A offers a well-rounded instruction set  
with 130 instruction types, including a comprehensive  
integer,floatingpoint,integer-to-floatingpointandfloating  
point-to-integer set, a variety of stack manipulation  
instructions, high level language support instructions  
such as Compare Between Bounds and Loop Control  
Instructions. It also offers some unique instructions such  
as vectored l/O, supports executive and user modes, and  
providesanescapemechanismwhichallowsuser-defined  
instructions using a coprocessor.  
Thebasicbuscycleis4clockslong. ThePACE1750Awill  
extend the cycle by insertion of wait states in the address  
and data phases (in response to RDYA and RDYD  
signals, repectively) and will hold the machine in HI-Z if  
this CPU has not acquired the bus. A typical non-bus  
cycle is three clocks long. However, variable length  
cyclesareusedforsuchrepetitiveoperationsasmultiply,  
divide, scale and normalize, reducing significantly the  
numberofCPUCLOCKSperoperationstepandresulting  
in very fast integer and floating point execution times.  
The chip includes 16 general purpose registers, 8 other  
user-accessible registers, and an array of real time  
application support resources, such as 2 programmable  
timers, a complete interrupt controller supporting 16  
Do c um e nt # MICRO-3 Re v. C  
Re vise d Oc to b e r 2005  
1234567...24

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