Datasheet > OXU210HP-LQAG

OXU210HP-LQAG

更新时间： 2024-11-19 21:21:59

品牌	Logo	应用领域
OXFORD		/
页数	文件大小	规格书
18页	398K
描述
Micro Peripheral IC,

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技术参数
数据手册

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OXU210HP-LQAG 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.65
Base Number Matches：	1

OXU210HP-LQAG 数据手册

Data Sheet

OXU210HP

USB2.0 High-Speed Host, Peripheral and OTG Controller

Features

High‐performance, high‐speed USB dual‐role (host/peripheral)

controller

Compatible with the Universal Serial Bus Specification, Revision 2.0

for high‐speed (480 Mb/s), full‐speed (12 Mb/s), and low‐speed

(1.5 Mb/s) operations

High‐speed optimized host controller with transaction translator

for complete backward compatibility with full‐speed and

low‐speed products

Two high‐speed USB ports; one port remains host while the other

can be configured as peripheral, host or OTG (dual role)

Simultaneous operation of both ports

Processor interface is either 16 bits (BGA) or configurable 16 or 32

bits (LQFP)

Fast microprocessor access cycle and double/multi buffering

support for USB transfers

Host interface contains support for common SoC DMA modes

including bursting and slave request/acknowledge protocols

Complete host, peripheral and OTG software solutions for

popular microprocessors using many of the most popular

operating systems

Advanced power management controls chip clocking and PHY

function for very low power consumption

Integrated on‐chip VBUS voltage comparator and 100 mA charge

pump

72 Kbytes of single‐port SRAM provides space for data structures

and buffer space for transfer data

True transfer level operation, with transaction scheduling and

handling (data sequence toggle, error retry, etc.), implemented in

hardware

Integrated PLL runs from a single 12‐MHz crystal or an external

12‐MHz clock source

DS-0037 Jun 06

External--Free Release

12 3 4 5 6 7...18

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