OP4018B1
Pb
• Complies with Directive 2002/95/EC (RoHS)
• Fundamental-Mode Oscillation at 718.864 MHz
• Quartz SAW Stabilized and Filtered “Diff Sine” Technology
• Voltage Tunable for Phase Lock Loop Operations
718.864 MHz
Optical
• Optical Timing Reference for Forward Error Correction Applications
Timing Clock
The output of this device is generated and filtered by narrowband quartz SAW elements at 718.864 MHz. The
configuration of this clock is intended to provide a pure signal for optical timing applications in noisy signal
environments. The Q/Qbar differential output swing of ±1 volt about 0 vdc has symmetry better than ±1% into
loads from 40 ohms to 70 ohms; determined by customer application. The long term frequency accuracy is
set by an external reference source allowing this device to complete a Phase Lock Loop design without the
usual noise and jitter problems associated with PLL’s.
Absolute Maximum Ratings
Rating
DC Suppy Voltage
Value
0 to 5.5
Units
VDC
Tune Voltage
Case Temperature
0 to 6
-55 to 100
VDC
°C
SMC-8A
Electrical Characteristics
Characteristic
Sym
Notes
1, 9
2
1
1, 8
Minimum
Typical
718.863785
Maximum
Units
MHz
ppm
VDC
%
Operating Frequency
Absolute Frequency
f
O
±50
1.8
±5
Tune Range
Tune Voltage
Tuning Linearity
2.4
3
3
5
100
100
150
0.6
Modulation Bandwidth
Tune DC resistance
Deviation Slope
Voltage into 50 Ω (VSWR≤1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
dBc/Hz@100Hz offset
1kHz offset
kHz
KΩ
ppm/volt
250
350
1.1
2:1
Q and Q Output
Phase Noise
Jitter
V
1,3
1,3
3, 4, 5
3, 4, 6
3, 4, 6, 7
V
P-P
O
49
51
-15
-65
-65
-95
%
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-70
-100
-125
-140
-150
-120
-135
10k offset
100k offset
Noise Floor
RMS Jitter (10kHz to 80MHz)
3, 4, 6, 7
0.5
-50
PS
P-P
dBc
200 mV
from 1MHz to ½ f on V
3
P-P
O
CC
Output DC Resistance (between Q & Q)
1, 3
1, 3
1, 3
50
3.135
KΩ
VDC
mA
°C
DC Power Supply
3.465
70
Operating Voltage
V
3.300
CC
Operating Current
Operating Ambient Temperature
I
CC
T
1, 3
0°C
+85°C
C
Lid Symbolization (YY=Year, WW=Week)
RFM OP4018B YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
COCOM CAUTION: Approval by the U.S. Department of Commerce is required prior to export of this device.
Notes:
1.
Unless otherwise noted, all specifications include any combination of load VSWR, VCC, and TC. In addition, Q and Q are terminated into 50 Ω loads to
ground. (See: Typical Test Circuit.)
2.
3.
4.
5.
6.
Customer useful tune range in excess of what part requires over temp, aging, pushing, pulling & accuracy.
The design, manufacturing process, and specifications of this device are subject to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q. (See: Timing Definitions.)
Jitter and other spurious outputs induced by externally generated electrical noise on V or mechanical vibration are not included in this specification, except
CC
where noted. External voltage regulation and careful PCB layout are recommended for optimum performance.
7.
8.
9.
Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples.
Linearity is a function of the percentage variation from a permitted linear deviation versus the amount of frequency tune range. See Linearity Definition.
One or more of the following United States patents apply: 4,616,197; 4,670,681; 4,760,352.
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©2008 by RF Monolithics, Inc.
OP4018B1 - 3/27/08