Preliminary
OP4017B
• Quartz SAW Stabilized Differential Output Technology
• Very Low Jitter Fundamental-Mode Operation at 777.60 MHz
• Voltage Tunable for Phase Locked Loop Applications
• Optical Timing Reference for Forward Error Correction Applications
777.60 MHz
Optical
Timing Clock
The OP4017B is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4017B are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4017B differential outputs
feature ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4017B is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
Value
0 to 5.5
Units
Vdc
Vdc
°C
DC Suppy Voltage
Tune Voltage
0 to 5.5
Case Temperature
-55 to 100
SMC-8
Electrical Characteristics
Characteristic
Sym
Notes
Minimum
Typical
Maximum
Units
777.6
Operating Frequency
Absolute Frequency
f
1
MHz
ppm
Vdc
%
O
±100
Tuning Range
2
Tuning Voltage
3.3
1
0
±5
50
Tuning Linearity
Modulation Bandwidth
1, 8
kHz
Q and Q Output
V
1,3
1,3
1.1
V
Voltage into 50 Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
0.60
49
O
P-P
2:1
51
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 6
%
Harmonic Spurious
Nonharmonic Spurious
@ 100 Hz offset
@ 1 kHz offset
dBc
-15
-60
dBc
Phase Noise
-70
-100
-125
-150
1
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
3, 6
3, 6
@ 10 kHz offset
Noise Floor
3, 6
3, 4, 6, 7
3, 4, 6, 7
Q and Q Jitter
RMS Jitter
No Noise on V
12
ps
ps
CC
P-P
P-P
200 mV
Noise, from 1 MHz to ½ f on V
CC
3
12
P-P
O
Output DC Resistance (between Q & Q)
KΩ
1, 3
1, 3
1, 3
1, 3
50
DC Power Supply
Operating Voltage
Operating Current
V
I
3.3 or 5.0
Vdc
mA
°C
3.13
5.25
70
CC
CC
Operating Case Temperature
T
-40°C
+85°C
C
Lid Symbolization (YY=Year, WW=Week)
RFM OP4017B YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
COCOM CAUTION: Approval by the U.S. Department of Commerce is required prior to export of this device.
Notes:
1. Unless otherwise noted, all specifications include the combined effects of load VSWR, V and T .
CC
C
2. Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, V , T and aging.
CC
C
3. The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
4. Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a V = 3.0 Vdc.
CC
5. Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
6. Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
7. Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 samples.
8. See Figure 4.
9. One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
www.RFM.com
E-mail: info@rfm.com
Page 1 of 2
©2008 by RF Monolithics, Inc.
OP4017B - 3/27/08