Low Noise, Precision, High Speed
a
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Operational Amplifier (A VCL 5)
OP37
FEATURES
The output stage has good load driving capability. A guaranteed
swing of 10 V into 600 Ω and low output distortion make the
OP37 an excellent choice for professional audio applications.
Low Noise, 80 nV p-p (0.1 Hz to 10 Hz)
3 nV/√Hz @ 1 kHz
Low Drift, 0.2 V/؇C
High Speed, 17 V/s Slew Rate
63 MHz Gain Bandwidth
Low Input Offset Voltage, 10 V
Excellent CMRR, 126 dB (Common-Voltage @ 11 V)
High Open-Loop Gain, 1.8 Million
Replaces 725, OP-07, SE5534 In Gains > 5
Available in Die Form
PSRR and CMRR exceed 120 dB. These characteristics, coupled
with long-term drift of 0.2 µV/month, allow the circuit designer
to achieve performance levels previously attained only by
discrete designs.
Low-cost, high-volume production of the OP37 is achieved by
using on-chip zener-zap trimming. This reliable and stable offset
trimming scheme has proved its effectiveness over many years of
production history.
GENERAL DESCRIPTION
The OP37 brings low-noise instrumentation-type performance to
such diverse applications as microphone, tapehead, and RIAA
phono preamplifiers, high-speed signal conditioning for data
acquisition systems, and wide-bandwidth instrumentation.
The OP37 provides the same high performance as the OP27,
but the design is optimized for circuits with gains greater than
five. This design change increases slew rate to 17 V/µs and
gain-bandwidth product to 63 MHz.
PIN CONNECTIONS
The OP37 provides the low offset and drift of the OP07
plus higher speed and lower noise. Offsets down to 25 µV and
drift of 0.6 µV/°C maximum make the OP37 ideal for preci-
sion instrumentation applications. Exceptionally low noise
(en= 3.5 nV/ @ 10 Hz), a low 1/f noise corner frequency of
2.7 Hz, and the high gain of 1.8 million, allow accurate
high-gain amplification of low-level signals.
8-Lead Hermetic DIP
(Z Suffix)
Epoxy Mini-DIP
(P Suffix)
8-Lead SO
(S Suffix)
The low input bias current of 10 nA and offset current of 7 nA
are achieved by using a bias-current cancellation circuit. Over
the military temperature range this typically holds IB and IOS
to 20 nA and 15 nA respectively.
1
2
3
4
8
7
6
5
V
TRIM
V
TRIM
–IN
+IN
V–
OS
OS
OP37
V+
OUT
NC
NC = NO CONNECT
SIMPLIFIED SCHEMATIC
V+
C2
R3
R4
1
8
Q6
Q22
Q46
C1
V
ADJ.
OS
R23 R24
Q24
R1*
R2*
Q21
Q23
R9
R12
Q20 Q19
OUTPUT
Q1A Q1B
Q2B Q2A
NON-INVERTING
INPUT (+)
C3
C4
R5
Q3
Q26
INVERTING
INPUT (–)
Q45
Q11 Q12
Q27
Q28
*R1 AND R2 ARE PERMANENTLY
ADJUSTED ATWAFERTEST FOR
MINIMUM OFFSETVOLTAGE.
V–
REV. A
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reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700
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© Analog Devices, Inc., 2002