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OP27GR PDF预览

OP27GR

更新时间: 2024-11-26 19:47:39
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
16页 364K
描述
IC OP-AMP, 100 uV OFFSET-MAX, 8 MHz BAND WIDTH, UUC5, 2.77 X 1.40 MM, DIE-5, Operational Amplifier

OP27GR 数据手册

 浏览型号OP27GR的Datasheet PDF文件第2页浏览型号OP27GR的Datasheet PDF文件第3页浏览型号OP27GR的Datasheet PDF文件第4页浏览型号OP27GR的Datasheet PDF文件第5页浏览型号OP27GR的Datasheet PDF文件第6页浏览型号OP27GR的Datasheet PDF文件第7页 
Low-Noise, Precision  
Operational Amplifier  
a
OP27  
PIN CONNECTIONS  
FEATURES  
Low Noise: 80 nV p-p (0.1 Hz to 10 Hz), 3 nV/  
Low Drift: 0.2 V/C  
High Speed: 2.8 V/s Slew Rate, 8 MHz Gain  
Bandwidth  
Hz  
TO-99  
(J-Suffix)  
BAL  
Low VOS: 10 V  
Excellent CMRR: 126 dB at VCM of 11 V  
High Open-Loop Gain: 1.8 Million  
Fits 725, OP07, 5534A Sockets  
Available in Die Form  
V+  
BAL 1  
OP27  
OUT  
–IN 2  
NC  
+IN 3  
GENERAL DESCRIPTION  
4V– (CASE)  
NC = NO CONNECT  
The OP27 precision operational amplifier combines the low  
offset and drift of the OP07 with both high speed and low noise.  
Offsets down to 25 µV and drift of 0.6 µV/°C maximum make  
the OP27 ideal for precision instrumentation applications.  
Exceptionally low noise, en = 3.5 nV/Hz, at 10 Hz, a low 1/f  
noise corner frequency of 2.7 Hz, and high gain (1.8 million),  
allow accurate high-gain amplification of low-level signals. A  
gain-bandwidth product of 8 MHz and a 2.8 V/µsec slew rate  
provides excellent dynamic accuracy in high-speed, data-  
acquisition systems.  
8-Pin Hermetic DIP  
(Z-Suffix)  
Epoxy Mini-DIP  
(P-Suffix)  
8-Pin SO  
(S-Suffix)  
A low input bias current of 10 nA is achieved by use of a  
bias-current-cancellation circuit. Over the military temperature  
range, this circuit typically holds IB and IOS to 20 nA and 15 nA,  
respectively.  
1
2
3
4
8
7
6
5
V
TRIM  
V
TRIM  
IN  
+IN  
V–  
OS  
OS  
OP27  
V+  
OUT  
NC  
The output stage has good load driving capability. A guaranteed  
swing of 10 V into 600 and low output distortion make the  
NC = NO CONNECT  
OP27 an excellent choice for professional audio applications.  
(Continued on page 7)  
V+  
C2  
R3  
R4  
1
8
Q6  
Q22  
Q46  
C1  
V
ADJ.  
OS  
R23 R24  
Q24  
R1*  
R2*  
Q21  
Q23  
R9  
Q20 Q19  
OUTPUT  
R12  
Q1A Q1B  
Q2B Q2A  
NONINVERTING  
INPUT (+)  
C3  
C4  
R5  
Q3  
Q26  
INVERTING  
INPUT ()  
Q45  
Q11 Q12  
Q27  
Q28  
*R1 AND R2 ARE PERMANENTLY  
ADJUSTED ATWAFERTEST FOR  
MINIMUM OFFSETVOLTAGE.  
V–  
Figure 1. Simplified Schematic  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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