Dual Precision JFET-Input
Operational Amplifier
a
OP215
FEATURES
High Slew Rate: 10 V/ꢀs Min
Fast Settling Time: 0.9 ꢀs to 0.1% Type
Low Input Offset Voltage Drift: 10 ꢀV/ꢁC Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125ꢁC)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/÷Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
GENERAL DESCRIPTION
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70∞C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
The OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low VOS, while a
bias-current compensation scheme gives a low input bias current
V+
NOTE
Q10
J5
Q5
R8
R7
Q1
R7, R8 ARE ELECTRONICALLY ADJUSTED
NULL
Q7
NULL
Q6
ON-CHIP FOR MINIMUM OFFSET VOLTAGE
Q9
J8 J7
Q19
R3
J6
Q24
R1
Q8
C2
R2
J1
J3
J2
Q17
NOMINV
INPUT+
J11
R13
Q22
Q25
–INV
7.4pF
Q2
INPUT
Q3
Q4
OUTPUT
R10
Q12
Q18
J10
Q23
R6
R5
3.6
kꢂ
3.6kꢂ
Q14
Q11
R4
C1
Q13
J9
Q21
R9
J4
Q15
Q20
7.4
pF
Q16
R11
R12
V–
Figure 1. Simplified Schematic (1/2 OP215)
REV. A
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may result from its use. No license is granted by implication or otherwise
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© Analog Devices, Inc., 2002