Ultraprecision
Operational Amplifier
OP177
FEATURES
PIN CONFIGURATION
Ultralow offset voltage
TA = 25°C, 25 μV maximum
Outstanding offset voltage drift 0.1 μV/°C maximum
Excellent open-loop gain and gain linearity
12 V/μV typical
1
2
3
4
8
7
6
5
V
TRIM
–IN
V
TRIM
OS
OS
OP177
V+
+IN
V–
OUT
NC
TOP VIEW
(Not to Scale)
NC = NO CONNECT
CMRR: 130 dB minimum
Figure 1. 8-Lead PDIP (P-Suffix),
8-Lead SOIC (S-Suffix)
PSRR: 115 dB minimum
Low supply current 2.0 mA maximum
Fits industry-standard precision op amp sockets
operational amplifier. The combination of outstanding
specifications of the OP177 ensures accurate performance in
high closed-loop gain applications.
GENERAL DESCRIPTION
The OP177 features one of the highest precision performance of
any op amp currently available. Offset voltage of the OP177 is
only 25 μV maximum at room temperature. The ultralow VOS of
the OP177 combines with its exceptional offset voltage drift
(TCVOS) of 0.1 μV/°C maximum to eliminate the need for
external VOS adjustment and increases system accuracy over
temperature.
This low noise, bipolar input op amp is also a cost effective
alternative to chopper-stabilized amplifiers. The OP177
provides chopper-type performance without the usual problems
of high noise, low frequency chopper spikes, large physical size,
limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 open-loop gain of 12 V/μV is maintained over the
full 10 V output range. CMRR of 130 dB minimum, PSRR of
120 dB minimum, and maximum supply current of 2 mA are
just a few examples of the excellent performance of this
The OP177 is offered in the −40°C to +85°C extended industrial
temperature ranges. This product is available in 8-lead PDIP, as
well as the space saving 8-lead SOIC.
FUNCTIONAL BLOCK DIAGRAM
V+
(OPTIONAL NULL)
R
*
R
*
2A
2B
C
1
R
7
R
R
1A
1B
Q
2B
19
R
Q
Q
10
9
9
Q
Q
12
11
Q
Q
Q
8
7
Q
Q
Q
6
Q
Q
OUTPUT
3
5
4
R
R
C
Q
3
C
3
2
17
NONINVERTING
INPUT
Q
R
27
26
25
10
Q
16
15
R
Q
1
R
5
Q
Q
Q
Q
20
21
23
24
Q
Q
22
4
INVERTING
INPUT
Q
2
Q
18
R
Q
14
Q
13
6
8
V–
*R AND R ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
2A 2B
Figure 2. Simplified Schematic
Rev. E
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