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CAT9554HV4I-G

更新时间： 2024-02-22 09:19:53
品牌 Logo 应用领域
安森美 - ONSEMI 并行IO端口微控制器和处理器外围集成电路
页数 文件大小 规格书
16页 172K
描述
8-bit I²C and SMBus I/O Port with Interrupt

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CAT9554HV4I-G 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：4 X 4 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-220, TQFN-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.34Is Samacsys：N
JESD-30 代码：S-XQCC-N16JESD-609代码：e4
长度：4 mm位数：8
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.16SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/5 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Parallel IO Port最大供电电压：5.5 V
最小供电电压：2.3 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

CAT9554HV4I-G 数据手册

 浏览型号CAT9554HV4I-G的Datasheet PDF文件第2页浏览型号CAT9554HV4I-G的Datasheet PDF文件第3页浏览型号CAT9554HV4I-G的Datasheet PDF文件第4页浏览型号CAT9554HV4I-G的Datasheet PDF文件第5页浏览型号CAT9554HV4I-G的Datasheet PDF文件第6页浏览型号CAT9554HV4I-G的Datasheet PDF文件第7页 
CAT9554, CAT9554A  
8-bit I²C and SMBus I/O Port with Interrupt  
FEATURES  
„ 400kHz I²C bus compatible (1)  
DESCRIPTION  
The CAT9554 and CAT9554A are CMOS devices that  
provide 8-bit parallel input/output port expansion for  
I²C and SMBus compatible applications. These I/O  
expanders provide a simple solution in applications  
where additional I/Os are needed: sensors, power  
switches, LEDs, pushbuttons, and fans.  
„ 2.3V to 5.5V operation  
„ Low stand-by current  
„ 5V tolerant I/Os  
„ 8 I/O pins that default to inputs at power-up  
„ High drive capability  
The CAT9554/9554A consist of an input port register,  
an output port register, a configuration register, a  
polarity inversion register and an I²C/SMBus-  
compatible serial interface.  
„ Individual I/O configuration  
„ Polarity inversion register  
„ Active low interrupt output  
„ Internal power-on reset  
Any of the eight I/Os can be configured as an input or  
output by writing to the configuration register. The  
system master can invert the CAT9554/9554A input  
data by writing to the active-high polarity inversion  
register.  
„ No glitch on power-up  
„ Noise filter on SDA/SCL inputs  
„ Cascadable up to 8 devices  
„ Industrial temperature range  
The CAT9554/9554A features an active low interrupt  
output which indicates to the system master that an  
input state has changed.  
„ RoHS-compliant 16-lead SOIC and TSSOP, and  
16-pad TQFN (4 x 4mm) packages  
The device’s extended addressing capability allows up  
to 8 devices to share the same bus. The CAT9554A is  
identical to the CAT9554 except the fixed part of the  
I²C slave address is different. This allows up to 16 of  
devices (eight CAT9554 and eight CAT9554A) to be  
connected on the same bus.  
APPLICATIONS  
„ White goods (dishwashers, washing machines)  
„ Handheld devices (cell phones, PDAs, digital  
cameras)  
„ Data Communications (routers, hubs and  
servers)  
For Ordering Information details, see page 15.  
BLOCK DIAGRAM (1)  
A0  
A1  
I/O  
I/O  
0
1
A2  
I/O  
I/O  
I/O  
2
3
4
8-BIT  
SCL  
INPUT/  
OUTPUT  
PORTS  
INPUT  
FILTER  
2
I C/SMBUS  
SDA  
CONTROL  
WRITE pulse  
READ pulse  
I/O  
5
I/O  
6
I/O  
7
V
CC  
POWER-ON  
RESET  
V
CC  
V
SS  
INT  
LP FILTER  
Notes:  
(1) All I/Os are set to inputs at RESET.  
© 2008 SCILLC. All rights reserved  
Characteristics subject to change without notice  
1
Doc. No. MD-9002, Rev. F  
 
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