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2N6073A PDF预览

2N6073A

更新时间: 2024-02-13 20:16:36
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发装置可控硅三端双向交流开关局域网
页数 文件大小 规格书
8页 123K
描述
Sensitive Gate Triacs

2N6073A 技术参数

生命周期:Obsolete包装说明:FLANGE MOUNT, R-PSFM-T3
Reach Compliance Code:unknownHTS代码:8541.30.00.80
风险等级:5.66Is Samacsys:N
其他特性:SENSITIVE GATE外壳连接:MAIN TERMINAL 2
配置:SINGLE最大直流栅极触发电流:30 mA
最大直流栅极触发电压:2.5 V最大维持电流:30 mA
JEDEC-95代码:TO-225AAJESD-30 代码:R-PSFM-T3
元件数量:1端子数量:3
最高工作温度:110 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT认证状态:Not Qualified
最大均方根通态电流:4 A重复峰值关态漏电流最大值:10 µA
断态重复峰值电压:400 V表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
触发设备类型:TRIACBase Number Matches:1

2N6073A 数据手册

 浏览型号2N6073A的Datasheet PDF文件第2页浏览型号2N6073A的Datasheet PDF文件第3页浏览型号2N6073A的Datasheet PDF文件第4页浏览型号2N6073A的Datasheet PDF文件第5页浏览型号2N6073A的Datasheet PDF文件第6页浏览型号2N6073A的Datasheet PDF文件第7页 
Preferred Device  
Silicon Bidirectional Thyristors  
Designed primarily for full-wave ac control applications, such as  
light dimmers, motor controls, heating controls and power supplies; or  
wherever full-wave silicon gate controlled solid-state devices are  
needed. Triac type thyristors switch from a blocking to a conducting  
state for either polarity of applied anode voltage with positive or  
negative gate triggering.  
http://onsemi.com  
TRIACS  
4 AMPERES RMS  
200 thru 600 VOLTS  
Sensitive Gate Triggering Uniquely Compatible for Direct Coupling  
to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit  
Logic Functions  
Gate Triggering 4 Mode — 2N6071A,B, 2N6073A,B, 2N6075A,B  
Blocking Voltages to 600 Volts  
All Diffused and Glass Passivated Junctions for Greater Parameter  
Uniformity and Stability  
MT2  
MT1  
Small, Rugged, Thermopad Construction for Low Thermal  
Resistance, High Heat Dissipation and Durability  
Device Marking: Device Type, e.g., 2N6071A, Date Code  
G
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
(1)  
*Peak Repetitive Off-State Voltage  
V
Volts  
DRM,  
(T = 40 to 110°C, Sine Wave,  
50 to 60 Hz, Gate Open)  
2N6071A,B  
V
RRM  
J
200  
400  
600  
2N6073A,B  
2N6075A,B  
3
2
1
*On-State RMS Current (T = 85°C)  
Full Cycle Sine Wave 50 to 60 Hz  
I
4.0  
Amps  
Amps  
C
T(RMS)  
TO–225AA  
(formerly TO–126)  
CASE 077  
*Peak Non–repetitive Surge Current  
I
30  
TSM  
(One Full cycle, 60 Hz, T = +110°C)  
J
STYLE 5  
2
2
Circuit Fusing Considerations  
(t = 8.3 ms)  
I t  
3.7  
10  
A s  
PIN ASSIGNMENT  
*Peak Gate Power  
P
Watts  
Watt  
Volts  
°C  
GM  
1
2
3
Main Terminal 1  
(Pulse Width 1.0 µs, T = 85°C)  
C
Main Terminal 2  
Gate  
*Average Gate Power  
P
0.5  
5.0  
G(AV)  
(t = 8.3 ms, T = 85°C)  
C
*Peak Gate Voltage  
V
GM  
(Pulse Width 1.0 µs, T = 85°C)  
C
ORDERING INFORMATION  
*Operating Junction Temperature Range  
T
J
–40 to  
+110  
Device  
2N6071A  
2N6071B  
2N6073A  
2N6073B  
Package  
TO225AA  
TO225AA  
TO225AA  
TO225AA  
Shipping  
500/Box  
500/Box  
500/Box  
500/Box  
*Storage Temperature Range  
T
–40 to  
+150  
°C  
stg  
(2)  
Mounting Torque (6-32 Screw)  
8.0  
in. lb.  
*Indicates JEDEC Registered Data.  
(1) V and V for all types can be applied on a continuous basis. Blocking  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
(2) Torque rating applies with use of a compression washer. Mounting torque in  
excess of 6 in. lb. does not appreciably lower case-to-sink thermal  
resistance. Main terminal 2 and heatsink contact pad are common.  
DRM RRM  
2N6075A  
2N6075B  
TO225AA  
TO225AA  
500/Box  
500/Box  
Preferred devices are recommended choices for future use  
and best overall value.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 3  
2N6071/D  

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