MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip–flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
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• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14174BCP
AWLYYWW
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
• Functional Equivalent to TTL 74174
1
16
SOIC–16
D SUFFIX
CASE 751B
14174B
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
1
SS
Symbol
Parameter
Value
Unit
V
16
V
DD
DC Supply Voltage Range
–0.5 to +18.0
SOEIAJ–16
F SUFFIX
CASE 966
MC14174B
ALYW
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
= Year
WW, W = Work Week
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
ORDERING INFORMATION
T
Lead Temperature
L
(8–Second Soldering)
Device
Package
PDIP–16
SOIC–16
Shipping
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14174BCP
MC14174BD
2000/Box
48/Rail
MC14174BDR2
SOIC–16 2500/Tape & Reel
MC14174BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
high–impedance circuit. For proper operation, V and V should be constrained
in
out
MC14174BFEL
to the range V v (V or V ) v V
.
SS
in
out
DD
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 4
MC14174B/D
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