5秒后页面跳转
11825-112 PDF预览

11825-112

更新时间: 2024-02-18 16:17:10
品牌 Logo 应用领域
安森美 - ONSEMI 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 180K
描述
48.00026MHz, OTHER CLOCK GENERATOR, PDSO16, 0.150 INCH, SOIC-16

11825-112 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:NJESD-30 代码:R-PDSO-G16
长度:9.9 mm端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:48.00026 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE主时钟/晶体标称频率:30 MHz
认证状态:Not Qualified座面最大高度:1.73 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

11825-112 数据手册

 浏览型号11825-112的Datasheet PDF文件第2页浏览型号11825-112的Datasheet PDF文件第3页浏览型号11825-112的Datasheet PDF文件第4页浏览型号11825-112的Datasheet PDF文件第5页浏览型号11825-112的Datasheet PDF文件第6页浏览型号11825-112的Datasheet PDF文件第7页 
FS6322-04  
Three-PLL Clock Generator IC  
1.0 Features  
2.0 Description  
The FS6322 is a ROM-based CMOS clock generator IC  
designed to minimize cost and component count in a va-  
riety of electronic systems.  
Three PLLs with deep reference, feedback, and post  
dividers to provide precision clock frequencies  
Multiple outputs provide several clocking options  
Outputs may be tristated for board testing  
Three low-jitter phase-locked loops (PLLs) drive up to five  
low-skew clock outputs to provide a high degree of flexi-  
bility. The device is packaged in a 16-pin SOIC to mini-  
mize board space.  
S0, S1, and S2 inputs modify output frequencies for  
design flexibility  
3.3V operation  
High-resolution divider capability permits generation of  
desired frequencies.  
Accepts 5 to 30MHz crystals (see Frequency Table  
for specific reference frequencies required)  
Custom frequency patterns, pinouts, and packages  
are available. Contact your local AMI Sales Repre-  
sentative for more information.  
Figure 1: Pin Configuration  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLK_C  
VDD  
OE  
S2  
VSS  
VDD  
S1  
XOUT/REFIN  
XIN  
S0  
CLK_E  
CLK_D  
CLK_F  
VSS  
CLK_A  
CLK_B  
16-pin (0.150”) SOIC  
Figure 2: Block Diagram  
OE  
XIN  
Crystal  
CLK_A  
CLK_B  
CLK_C  
CLK_D  
CLK_E  
CLK_F  
Oscillator  
XOUT  
PLL A  
PLL B  
PLL C  
Clock  
Logic  
Device  
Control  
S2:S0  
FS6322-04  
This document contains information on a product under development. American Microsystems, Inc. reserves the right to change or discontinue this product without notice.  
3.1.02  
ISO9001  

与11825-112相关器件

型号 品牌 描述 获取价格 数据表
1-1825143-1 MACOM Switches Core Program

获取价格

1-1825190-0 TE SHUNT, DIP, PROGRAMMABLE

获取价格

11825-803 AMI Clock Generator, 83.00071MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

获取价格

11825-808 ETC Three-PLL Clock Generator IC

获取价格

11825-813 AMI Clock Generator, 83.00071MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

获取价格

11825-814 AMI Clock Generator, 54MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

获取价格