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OMAPL138B-EP

更新时间： 2024-09-25 11:58:19
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德州仪器 - TI /
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282页 1975K
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OMAPL138B C6-Integra™ DSPARM® Processor

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OMAPL138B-EP  
www.ti.com  
SPRS815B –DECEMBER 2011–REVISED MARCH 2012  
OMAPL138B C6-Integra™ DSP+ARM® Processor  
Check for Samples: OMAPL138B-EP  
1 OMAPL138B C6-Integra™ DSP+ARM® Processor  
1.1 Features  
1
• Highlights  
• C674x Two Level Cache Memory Architecture  
– Dual Core SoC  
– 32K-Byte L1P Program RAM/Cache  
– 32K-Byte L1D Data RAM/Cache  
– 256K-Byte L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
•
•
345-MHz ARM926EJ-S™ RISC MPU  
345-MHz C674x Fixed/Floating-Point VLIW  
DSP  
– Supports TI’s Basic Secure Boot  
– Enhanced Direct-Memory-Access Controller  
(EDMA3)  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– 2 Channel Controllers  
– Serial ATA (SATA) Controller  
– 3 Transfer Controllers  
– DDR2/Mobile DDR Memory Controller  
– Two Multimedia Card (MMC)/Secure Digital  
(SD) Card Interface  
– LCD Controller  
– Video Port Interface (VPIF)  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
– Programmable Transfer Burst Size  
• TMS320C674x Floating-Point VLIW DSP Core  
– Load-Store Architecture With Non-Aligned  
Support  
– 64 General-Purpose Registers (32 Bit)  
– Six ALU (32-/40-Bit) Functional Units  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– Programmable Real-Time Unit Subsystem  
– Three Configurable UART Modules  
– USB 1.1 OHCI (Host) With Integrated PHY  
– One Multichannel Audio Serial Port  
– Two Multichannel Buffered Serial Ports  
• Dual Core SoC  
•
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
•
•
Supports up to Four SP Additions Per  
Clock, Four DP Additions Every 2 Clocks  
Supports up to Two Floating Point (SP or  
DP) Reciprocal Approximation (RCPxP)  
and Square-Root Reciprocal  
– 345-MHz ARM926EJ-S™ RISC MPU  
– 345-MHz C674x Fixed/Floating-Point VLIW  
DSP  
• ARM926EJ-S Core  
Approximation (RSQRxP) Operations Per  
Cycle  
– Two Multiply Functional Units  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– DSP Instruction Extensions  
– Single Cycle MAC  
•
Mixed-Precision IEEE Floating Point  
Multiply Supported up to:  
– ARM® Jazelle® Technology  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
–
–
–
–
2 SP x SP → SP Per Clock  
2 SP x SP → DP Every Two Clocks  
2 SP x DP → DP Every Three Clocks  
2 DP x DP → DP Every Four Clocks  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
•
Fixed Point Multiply Supports Two 32 x  
32-Bit Multiplies, Four 16 x 16-Bit  
Multiplies, or Eight 8 x 8-Bit Multiplies per  
Clock Cycle, and Complex Multiples  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
• C674x™ Instruction Set Features  
– Superset of the C67x+™ and C64x+™ ISAs  
– Up to 3648/2746 C674x MIPS/MFLOPS  
– Byte-Addressable (8-/16-/32-/64-Bit Data)  
– 8-Bit Overflow Protection  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– Exceptions Support for Error Detection and  
– Compact 16-Bit Instructions  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2011–2012, Texas Instruments Incorporated  
 
 
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