OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
www.ti.com
SPRS599–JUNE 2009
1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
1.1 Features
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Additional C64x+™ Enhancements
•
OMAP3525 and OMAP3530 Applications
Processors:
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
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OMAP™ 3 Architecture
MPU Subsystem
•
Hardware Support for Modulo Loop
Operation
•
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600-MHz ARM Cortex™-A8 Core
NEON™ SIMD Coprocessor
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C64x+ L1/L2 Memory Architecture
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High Performance Image, Video, Audio
(IVA2.2™) Accelerator Subsystem
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32K-Byte L1P Program RAM/Cache (Direct
Mapped)
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
64K-Byte L2 Unified Mapped RAM/Cache
(4-Way Set-Associative)
32K-Byte L2 Shared SRAM and 16K-Byte L2
ROM
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•
430-MHz TMS320C64x+™ DSP Core
Enhanced Direct Memory Access
(EDMA) Controller (128 Independent
Channels)
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Video Hardware Accelerators
POWERVR SGX™ 2D/3D Graphics
Accelerator (OMAP3530 Device Only)
•
C64x+ Instruction Set Features
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Tile Based Architecture Delivering up to
10 MPoly/sec
Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating
Pixel and Vertex Shader Functionality
Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load
Balancing, and Power Management
Programmable High Quality Image
Anti-Aliasing
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation. Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support Complex
Multiplies
•
•
•
•
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ARM Cortex™-A8 Core
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ARMv7 Architecture
•
•
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Trust Zone®
Thumb®-2
MMU Enhancements
–
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Fully Software-Compatible With C64x and
ARM9™
Commercial and Extended Temperature
Grades
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In-Order, Dual-Issue, Superscalar
Microprocessor Core
•
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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NEON™ Multimedia Architecture
Over 2x Performance of ARMv6 SIMD
Supports Both Integer and Floating Point
SIMD
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Eight Highly Independent Functional Units
•
+Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
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Jazelle® RCT Execution Environment
Architecture
Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
•
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Embedded Trace Macrocell (ETM) Support
for Non-Invasive Debug
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Load-Store Architecture With Non-Aligned
Support
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
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ARM Cortex™-A8 Memory Architecture:
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16K-Byte Instruction Cache (4-Way
Set-Associative)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
POWERVR SGX is a trademark of Imagination Technologies Ltd.
OMAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2009, Texas Instruments Incorporated
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