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OMAP3530ECBB PDF预览

OMAP3530ECBB

更新时间： 2024-02-02 14:48:15
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路
页数 文件大小 规格书
239页 3505K
描述
应用处理器 | CBB | 515 | 0 to 90

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OMAP3530ECBB 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LFBGA, BGA423,24X24,25
针数：423Reach Compliance Code：compliant
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：2.24JESD-30 代码：S-PBGA-B423
JESD-609代码：e1长度：16 mm
湿度敏感等级：4端子数量：423
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA423,24X24,25封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.1,1.2,1.8,1.8/3 V认证状态：Not Qualified
座面最大高度：1.4 mm子类别：Graphics Processors
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.65 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：16 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

OMAP3530ECBB 数据手册

 浏览型号OMAP3530ECBB的Datasheet PDF文件第2页浏览型号OMAP3530ECBB的Datasheet PDF文件第3页浏览型号OMAP3530ECBB的Datasheet PDF文件第4页浏览型号OMAP3530ECBB的Datasheet PDF文件第5页浏览型号OMAP3530ECBB的Datasheet PDF文件第6页浏览型号OMAP3530ECBB的Datasheet PDF文件第7页 
OMAP3525-HiRel and OMAP3530-HiRel Applications Processors  
www.ti.com  
SPRS599–JUNE 2009  
1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors  
1.1 Features  
–
Additional C64x+™ Enhancements  
•
OMAP3525 and OMAP3530 Applications  
Processors:  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
–
–
OMAP™ 3 Architecture  
MPU Subsystem  
•
Hardware Support for Modulo Loop  
Operation  
•
•
600-MHz ARM Cortex™-A8 Core  
NEON™ SIMD Coprocessor  
•
C64x+ L1/L2 Memory Architecture  
–
–
High Performance Image, Video, Audio  
(IVA2.2™) Accelerator Subsystem  
–
–
–
–
32K-Byte L1P Program RAM/Cache (Direct  
Mapped)  
80K-Byte L1D Data RAM/Cache (2-Way  
Set-Associative)  
64K-Byte L2 Unified Mapped RAM/Cache  
(4-Way Set-Associative)  
32K-Byte L2 Shared SRAM and 16K-Byte L2  
ROM  
•
•
430-MHz TMS320C64x+™ DSP Core  
Enhanced Direct Memory Access  
(EDMA) Controller (128 Independent  
Channels)  
•
Video Hardware Accelerators  
POWERVR SGX™ 2D/3D Graphics  
Accelerator (OMAP3530 Device Only)  
•
C64x+ Instruction Set Features  
•
Tile Based Architecture Delivering up to  
10 MPoly/sec  
Universal Scalable Shader Engine:  
Multi-threaded Engine Incorporating  
Pixel and Vertex Shader Functionality  
Industry Standard API Support:  
OpenGLES 1.1 and 2.0, OpenVG1.0  
Fine Grained Task Switching, Load  
Balancing, and Power Management  
Programmable High Quality Image  
Anti-Aliasing  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation. Bit-Counting  
Compact 16-Bit Instructions  
Additional Instructions to Support Complex  
Multiplies  
•
•
•
•
•
ARM Cortex™-A8 Core  
–
ARMv7 Architecture  
•
•
•
Trust Zone®  
Thumb®-2  
MMU Enhancements  
–
–
Fully Software-Compatible With C64x and  
ARM9™  
Commercial and Extended Temperature  
Grades  
–
In-Order, Dual-Issue, Superscalar  
Microprocessor Core  
•
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
–
–
–
NEON™ Multimedia Architecture  
Over 2x Performance of ARMv6 SIMD  
Supports Both Integer and Floating Point  
SIMD  
–
Eight Highly Independent Functional Units  
•
+Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
–
Jazelle® RCT Execution Environment  
Architecture  
Dynamic Branch Prediction with Branch  
Target Address Cache, Global History  
Buffer, and 8-Entry Return Stack  
•
–
Embedded Trace Macrocell (ETM) Support  
for Non-Invasive Debug  
–
Load-Store Architecture With Non-Aligned  
Support  
–
–
–
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
•
ARM Cortex™-A8 Memory Architecture:  
–
16K-Byte Instruction Cache (4-Way  
Set-Associative)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
POWERVR SGX is a trademark of Imagination Technologies Ltd.  
OMAP is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2009, Texas Instruments Incorporated  
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