OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
1 OMAP3515/03 Applications Processor
1.1 Features
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External Memory Interfaces:
•
OMAP3515/03 Applications Processor:
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SDRAM Controller (SDRC)
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OMAP™ 3 Architecture
MPU Subsystem
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16, 32-bit Memory Controller With
2G-Byte Total Address Space
Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
SDRAM Memory Scheduler (SMS) and
Rotation Engine
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600-MHz ARM Cortex™-A8 Core
NEON™ SIMD Coprocessor
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2D/3D Graphics Accelerator (OMAP3515
Device Only)
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Tile Based Architecture Delivering 10
MPoly/sec
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General Purpose Memory Controller
(GPMC)
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Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating
Pixel and Vertex Shader Functionality
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16-bit Wide Multiplexed Address/Data
Bus
Up to 8 Chip Select Pins With 129M-Byte
Address Space per Chip Select Pin
Glueless Interface to NOR Flash, NAND
Flash (With ECC Hamming Code
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Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0 and
Direct3D Mobile
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Fine Grained Task Switching, Load
Balancing, and Power Management
Programmable High Quality Image
Anti-Aliasing
Calculation), SRAM and Pseudo-SRAM
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Flexible Asynchronous Protocol Control
for Interface to Custom Logic (FPGA,
CPLD, ASICs, etc.)
Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
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Fully Software-Compatible With ARM9™
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ARM Cortex™-A8 Core
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ARMv7 Architecture
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System Direct Memory Access (sDMA)
Controller (32 Logical Channels With
Configurable Priority)
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Trust Zone®
Thumb®-2
MMU Enhancements
Camera Image Signal Processing (ISP)
In-Order, Dual-Issue, Superscalar
Microprocessor Core
NEON™ Multimedia Architecture
Over 2x Performance of ARMv6 SIMD
Supports Both Integer and Floating Point
SIMD
Jazelle® RCT Execution Environment
Architecture
Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
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CCD and CMOS Imager Interface
Memory Data Input
RAW Data Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
A-Law Compression and Decompression
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module/Auto-Exposure,
Auto-White Balance, and Auto-Focus
Engine
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Embedded Trace Macrocell (ETM) Support
for Non-Invasive Debug
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ARM Cortex™-A8 Memory Architecture:
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Resize Engine
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16K-Byte Instruction Cache (4-Way
Set-Associative)
16K-Byte Data Cache (4-Way
Set-Associative)
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Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
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Display Subsystem
Parallel Digital Output
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256K-Byte L2 Cache
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Up to 24-Bit RGB
HD Maximum Resolution
Endianess: ARM Big Endian
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
is a trademark of ~ Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008, Texas Instruments Incorporated
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