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OL2311AHN PDF预览

OL2311AHN

更新时间: 2024-11-09 21:15:59
品牌 Logo 应用领域
恩智浦 - NXP 电信电信集成电路
页数 文件大小 规格书
133页 1625K
描述
SPECIALTY TELECOM CIRCUIT, PQCC32, 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT617-3, HVQFN-32

OL2311AHN 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT617-3, HVQFN-32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.67
JESD-30 代码:S-PQCC-N32长度:5 mm
湿度敏感等级:3功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-25 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
座面最大高度:0.85 mm标称供电电压:2.7 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
Base Number Matches:1

OL2311AHN 数据手册

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OL2311  
Highly integrated single-chip sub 1 GHz RF receiver  
Rev. 1 — 8 December 2011  
Product data sheet  
1. General description  
A highly integrated single-chip receiver solution, the OL2311 is ideally suited to telemetry  
applications operating in the ISM/SRD bands. The small form factor, low power  
consumption and wide supply voltage range make this device suitable for use in battery  
powered, handheld devices and their counter parts.  
The device utilizes a fully integrated, programmable fractional-N PLL (including loop filter)  
to control the Local Oscillator (LO), thus supporting multi-channel operation and  
frequency hopping schemes. This feature also allows programmable frequency steps for  
crystal (XTAL) drift compensation.  
The device is based on a low IF direct conversion receiver architecture, with on-chip IF  
filtering and programmable channel bandwidth. After filtering and amplification the  
quadrature signals are digitized, demodulated and processed in the digital domain.  
Baseband processing of the received signal comprises a demodulator, a data-slicer and  
clock recovery followed by a Manchester decoder. Automated signal signature recognition  
units are available to allow simple, fast and reliable data reception.  
The device is controlled via a three-wire serial interface (SPI) with data input and output,  
data clock and interface enable. The interface can be configured to a full SPI interface  
with separate data and clock pins. Additional pins are available to access internal signals  
in real-time.  
2. Features and benefits  
Highly integrated solution for the 315/434/868/915 MHz band  
Very few external components required  
Complies with ETSI EN300-220/FCC part 15 standards  
Near zero-IF RX architecture  
On-chip channel filtering with automatic calibration supported to provide stable cut-off  
frequencies and filter roll-off  
Multi-channel operation by fully integrated fractional-N PLL with on-chip loop filter  
Automatic VCO sub-band selection and calibration to reduce PLL loop bandwidth  
variation  
Digital RSSI with a configurable threshold  
Onboard Signal Signature Recognition Unit with Preamble Pattern Recognition  
Configurable polling timer with 2% absolute accuracy  
Level Sensitive Data slicer with self-adjusting threshold  
Low power Consumption (RX 16mA), with ultra Low 0.5µA standby current and  
configurable polling timer  
 
 

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