Product Brief
Marvell® OCTEON Fusion® CNF95xx Family
4G/5G Macro Cell Baseband Processor
Overview
• Marvell is the industry leader in 5G macro cell base station
silicon
CNF95xx baseband processors are well suited for both
traditional all-in-one base station designs as well as emerging
ORAN-defined split architecture base stations. An OCTEON
Fusion CNF95xx distributed unit (DU) combined with a
complementary OCTEON CN9xxx network processor central
unit (CU) provides a compelling price/performance advantage
over competing solutions. In addition, CNF95xx baseband
processors support both mid-band (sub-7GHz) and mmWave
radio frequencies making them suitable for 5G deployments
in any geography worldwide.
• CNF95xx is already in volume production with leading
tier 1 OEMS
• CNF95xx may be combined with other Marvell processors
(OCTEON, ThunderX, Prestera) to provide network
infrastructure OEMs with complete RAN solutions from
one supplier
• Marvell is willing to engage with OEMs to design semi-custom
CNF95xx variants, either by incorporating the OEM’s IP blocks
or by modifying the design for related PHY processing
functions
CNF95xx is a lower cost and lower power alternative to the
FPGA-based solutions found in the 4G/5G infrastructure
market. These third-generation OCTEON Fusion processors
have been ptimized for 5G PHY Layer performance but retain
a degree of programmability to support future enhancements
to the 3GPP 5G specification.
The OCTEON Fusion® CNF95xx family of 4G/5G baseband
processors is targeted at top tier telecommunication
equipment manufacturers. With a specific focus on running 5G
and 4G layer 1 processing for very high throughput macro cell
base stations, CNF95xx is the industry’s only macro cell
merchant silicon available in the market. CNF95xx is currently
in volume production with leading tier 1 OEMs.
Marvell is receptive to the possibility of developing customer-
specific variants of the CNF95xx processor for OEMs who would
like their own IP blocks embedded within the chip.
Block Diagram
OCTEON TX2
CPU
Subsystem
Fronthaul
Backhaul
PHY
Subsystem
I/O
Subsystem
CPU Memory
DDR
Subsystem