Datasheet > OC-32B-100T-1.544MHZ

OC-32B-100T-1.544MHZ

更新时间： 2025-06-14 19:49:35

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Oscillator

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OC-32B-100T-1.544MHZ 技术参数

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.57	Base Number Matches：	1

OC-32B-100T-1.544MHZ 数据手册

C A L I B E R

E l e c t r o n i c s I n c .

Lead-Free

RoHS Compliant

OC-32 Series

3.2X2.5X1.2mm / SMD / HCMOS/TTL Oscillator

PART NUMBERING GUIDE

Environmental/Mechanical Specifications on page F5

OC-32A- 100 48 A T - 30.000MHz

Package

OC-32

Pin One Connection

T = Tri State Enable High

= 3.3Vdc

OC-32A = 1.8Vdc

OC-32B = 2.5Vdc

Output Symmetry

Blank = 40/60%, A = 45/55%

Operating Temperature Range

Blank = -10°C to 70°C, 27 = -20°C to 70°C, 48 = -40°C to 85°C

Inclusive Stability

100= +/-100ppm, 50= +/-50ppm, 30= +/-30ppm, 25= +/-25ppm,

20= +/-20ppm

ELECTRICAL SPECIFICATIONS

Frequency Range

Revision: 2006-C

1.544MHz to 80.000MHz / 32.768kHz (@ 3.3V)

-10°C to 70°C / -20°C to 70°C / -40°C to 85°C

-55°C to 125°C

Operating Temperature Range

Storage Temperature Range

Supply Voltage

A=1.8Vdc / B=2.5Vdc / BLANK=3.3Vdc ±10%

1.544MHz to 32.000MHz and 32.768kHz

36,001MHz to 70.000MHz

70.001MHz to 125.000MHz

2mA Maximum

3mA Maximum

4mA Maximum

(3.3v, 2.5v, 1.8v)

Input Current

Inclusive of Operating Temperature Range, Supply

Voltage and Load

±100ppm, ±50ppm, ±30ppm, ±25ppm, ±20ppm,

(±50ppm for 32.768kHz only)

Frequency Tolerance / Stability

w/HCMOS or TTL Load

wHCMOS or TTL Load

90% of Vdd Min. / Ioh=-8mA

10% of Vdd Max. / Iol=8mA

Output Voltage Logic High (Voh)

Output Voltage Logic Low (Vol)

Rise / Fall Time

10% to 90% of Waveform w/HCMOS Load; 0.4Vdc to 2.4V w/TTL Load / 6nSec Max.

@1.4Vdc w/TTL Load; @50% w/HCMOS Load

@1.4Vdc w/TTL Load or w/HCMOS Load

50 ±10% (Standard)

50±5% (Optional)

Duty Cycle

15pF HCMOS Load

Load Drive Capability

Pin 1 Tristate Function

Pin 1 = H or Open / Output Active at pin 3

Pin 1 = L / High Impedance at pin 3

±5ppm / year Maximum

10mSeconds Maximum

±250pSeconds Maximum

±50pSeconds Maximum

Aging (@ 25°C)

Start Up Time

Absolute Clock Jitter

One Sigma Clock Jitter

NOTE: A 0.01uF bypass capacitor should be placed between Vdd (Pin 4) and GND (Pin 2) to minimize power supply line noise.

MECHANICAL DIMENSIONS

Marking Guide

Recommended Solder Pattern

All Dimensions in mm.

Metal

0.9

±0.2

(X4 plcs.)

2.5

± 0.15

0.95

Line 1: A, B or Blank - Frequency

Line 2: CEI YM

2.20

±0.15

1.20

3.2

± 0.15

= Voltage designator

CEI = Caliber Electronics Inc.

YM = Date Code (Year / Month)

2.2

1.00±

0.15

Ceramic

1.2

Max

1.75

Pin 1: Tri-State

Pin 2: Case Ground

Pin 3: Output

Pin 4: Supply Voltage (3.3v, 2.5v, 1.8v)

TEL 949-366-8700

FAX 949-366-8707

WEB http://www.caliberelectronics.com

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