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PPC5602BFVLH4R

更新时间: 2023-12-18 00:00:00
品牌 Logo 应用领域
恩智浦 - NXP PC微控制器
页数 文件大小 规格书
109页 1086K
描述
MPC5604B/C Microcontroller Data Sheet

PPC5602BFVLH4R 数据手册

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NXP Semiconductors  
Data Sheet: Technical Data  
Document Number: MPC5604BC  
Rev. 14, 11/2017  
MPC5604B/C  
MPC5604B/C  
Microcontroller Data Sheet  
208 MAPBGA (17 x 17 x 1.7 mm)  
144 LQFP (20 x 20 x 1.4 mm)  
100 LQFP (14 x 14 x 1.4 mm)  
64 LQFP (10 x 10 x 1.4 mm)  
Features  
• Up to 6 enhanced full CAN (FlexCAN) modules with  
configurable buffers  
• Single issue, 32-bit CPU core complex (e200z0)  
– Compliant with the Power Architecture® embedded  
category  
• 1 inter IC communication interface (I2C) module  
• Up to 123 configurable general purpose pins supporting  
input and output operations (package dependent)  
• Real Time Counter (RTC) with clock source from128 kHz  
or 16 MHz internal RC oscillator supporting autonomous  
wakeup with 1 ms resolution with max timeout of 2  
seconds  
– Includes an instruction set enhancement allowing  
variable length encoding (VLE) for code size footprint  
reduction. With the optional encoding of mixed 16-bit  
and 32-bit instructions, it is possible to achieve  
significant code size footprint reduction.  
• Up to 512 KB on-chip code flash supported with the flash  
controller and ECC  
• Up to 6 periodic interrupt timers (PIT) with 32-bit counter  
resolution  
• 64 (4 × 16) KB on-chip data flash memory with ECC  
• Up to 48 KB on-chip SRAM with ECC  
• Memory protection unit (MPU) with 8 region descriptors  
and 32-byte region granularity  
• Interrupt controller (INTC) with 148 interrupt vectors,  
including 16 external interrupt sources and 18 external  
interrupt/wakeup sources  
• 1 System Module Timer (STM)  
• Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus standard  
• Device/board boundary Scan testing supported with per  
Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)  
• On-chip voltage regulator (VREG) for regulation of  
input supply for all internal levels  
• Frequency modulated phase-locked loop (FMPLL)  
• Crossbar switch architecture for concurrent access to  
peripherals, flash memory, or RAM from multiple bus  
masters  
• Boot assist module (BAM) supports internal flash  
programming via a serial link (CAN or SCI)  
• Timer supports input/output channels providing a range of  
16-bit input capture, output compare, and pulse width  
modulation functions (eMIOS-lite)  
• 10-bit analog-to-digital converter (ADC)  
• 3 serial peripheral interface (DSPI) modules  
• Up to 4 serial communication interface (LINFlex)  
modules  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  

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