Datasheet > NTE849

NTE849

更新时间： 2024-10-31 22:50:47

品牌	Logo	应用领域
NTE		电视
页数	文件大小	规格书
5页	37K
描述
Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System

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NTE849 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP-14	针数：	14
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.61
应用：	TV	消隐输出：	YES
商用集成电路类型：	HORIZ/VERT DEFLECTION IC	JESD-30 代码：	R-PDIP-T14
功能数量：	1	端子数量：	14
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
最大供电电压 (Vsup)：	13.2 V	最小供电电压 (Vsup)：	10.8 V
表面贴装：	NO	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子位置：	DUAL
Base Number Matches：	1

NTE849 数据手册

NTE849

Integrated Circuit

TV Horizontal/Vertical Countdown

Digital Sync System

Description:

The NTE849 is an integrated circuit in a 14–Lead DIP type package designed for use in TV horizontal/

vetical countdown digital sync systems. In some video playback units, there are incorrect frequency

relationships between horizontal and field frequencies. Automatic forced asynchronous mode elimi-

nates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.

Automatic standard mode occurs upon detection of nine or more equalizing pulses during a six–line–

width vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and

internal counter output. Standard mode is retained for seven fields of missing or mutilated vertical

sync pulses.

If two or more noise pulses are detected at Pin12 during a 384–line active scan time, a noise detector

reverts the system to standard mode at the next field of coincidence (without seven fields of coinci-

dene delay). Thus, the unit stays in standard mode during tuner channel changes.

An automatic mode–recognition system places the unit in standard mode for NTSC signals or into

non–synchronous mode for non–standard sync signals.

An external oscillator (NTE701) supplies an input to Pin9 that is 32 times the horizontal rate. An inter-

nal divide–by–16 counter converts this input (32f_H) to 2f_Hfor use elsewhere. This 32f_Hsignal is further

divided to f_H, which is available at Pin11 to drive the horizontal deflection circuits. A divide–by–525

counter further divides the 2f_Hsignal to generate the vertical ramp generator timing pulses and the

vertical blanking pulse.

A phasing circuit (part of the mode recognition and vertical regeneration circuits) insures that the 525

counter is reset in coincidence with the vertical sync. It does this by comparing the internally gener-

ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12. The automatic

mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the non–

synchronous mode for non–standard sync signals such as video games. An input control signal (or

no connection) at Pin8 places the NTE849 into non–synchronous operation.

A phasing and timing logic circuit checks to see if the line counter is in sync with the IV signal at Pin12.

Seven consecutive fields of in–phase coincidence with the IV signal are needed to achieve standard

mode in unless two or more noise pulses are de–detected at input Pin12 during the active scan time.

In this case, normal mode will be acquired in one field.

12 3 4 5

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NTE849 替代型号

型号	品牌	替代类型	描述	数据表
TDA9108	STMICROELECTRONICS	功能相似	MONITOR HORIZONTAL PROCESSOR

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