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NTE4531BT PDF预览

NTE4531BT

更新时间: 2024-11-02 20:02:03
品牌 Logo 应用领域
NTE 光电二极管逻辑集成电路
页数 文件大小 规格书
4页 73K
描述
Parity Generator/Checker,

NTE4531BT 技术参数

生命周期:Active包装说明:LSOP,
Reach Compliance Code:unknown风险等级:5.77
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
长度:9.9 mm逻辑集成电路类型:PARITY GENERATOR/CHECKER
位数:12功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:CONFIGURABLE
封装主体材料:PLASTIC/EPOXY封装代码:LSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE
传播延迟(tpd):750 ns座面最大高度:1.682 mm
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.91 mm
Base Number Matches:1

NTE4531BT 数据手册

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NTE4531B & NTE4531BT  
Integrated Circuit  
CMOS, 12Bit Parity Tree  
Description:  
The NTE4531B (16Lead DIP) and NTE4531BT (SOIC16) are 12bit parity tree devices constructed  
with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. The  
circuit consists of 12 databit inputs (D0 thru D11), an even or odd parity selection input (W) and an  
output (Q). The parity selection input can be considered as an additional bit. Words of less than 13 bits  
can generate an even or odd parity output if the remaining inputs are selected to contain an even or odd  
number of ones, respectively. Words of greater than 12bits can be accommodated by cascading other  
NTE4531B devices by using the W input. Applications include checking or including a redundant (parity)  
bit to a word for error detection/correction systems, controller for remote digital sensors or switches (di-  
gital event detection/correction), or as a multiple input summer without carries.  
Features:  
D Noise Immunity = 45% of VDD (Typ)  
D Supply Voltage Range: 3Vdc to 18Vdc  
D All Output Buffered  
D Capable of Driving Two LowPower TTL Loads, One LowPower Schottky TTL Load or Two  
HTL Loads Over the Rated Temperature Range  
D Quiescent Current = 5nA/Package (Typ) at 5Vdc  
D Variable Word Length  
D Diode Protection on All Inputs  
Absolute Maximum Ratings: (Voltages referenced to VSS)  
DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to +18.0V  
Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to VDD to +0.5V  
DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA  
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55° to +125°C  
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65° to +150°C  

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