NTE4518B & NTE4518BT
Integrated Circuit
CMOS, Dual BCD Up Counter Counter
Description:
The NTE4518B (16−Lead DIP) and NTE4518BT (SOIC−16) are dual BCD up counters constructed with
MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each con-
sists of two identical, independent, internally synchronous 4−stage counters. The counter stages are
type D flip−flops, with interchangeable Clock and Enable lines for incrementing on either the positive−
going or negative−going transition as required when cascading multiple stages. Each counter can be
cleared by applying a high level on the Reset line. In addition, the NTE1458B/BT will count out of all
undefined states within two clock periods.
These complementary MOS up counters find primary use in multi−stage synchronous or ripple counting
applications requiring low power dissipation and/or high noise immunity.
Features:
D Quiescent Current = 5nA/Package (Typ) at 5Vdc
D Noise Immunity = 45% of VDD (Typ)
D Diode Protection on All Inputs
D Supply Voltage Range = 3Vdc to 18Vdc
D Low Input Capacitance = 5pF (Typ)
D Internally Synchronous for High Internal and External Speeds
D Logic Edge−Clocked Design − Incremental on Positive Transition of Clock or
Negative Transition Enable
D 6Mhz Counting Rate
D Asynchronous Preset Enable Operation
D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two
HTL Loads Over the Rated Temperature Range
Absolute Maximum Ratings: (Voltages Referenced to VSS, Note 1)
DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V
Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD + 0.5V
DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C
Note 1. These devices contain circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance cir-
cuit. For proper operation is is recommended that Vin and Vout be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD).