Datasheet > NTE4510BT

NTE4510BT

更新时间： 2024-02-13 04:04:39

品牌	Logo	应用领域
NTE		逻辑集成电路
页数	文件大小	规格书
5页	76K
描述
Decade Counter,

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技术参数
数据手册

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NTE4510BT 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
逻辑集成电路类型：	DECADE COUNTER	Base Number Matches：	1

NTE4510BT 数据手册

NTE4510B & NTE4510BT

Integrated Circuit

CMOS, Presettable Up/Down BCD Counter

Description:

The NTE4510B (16−Lead DIP) and NTE4510BT (SOIC−16) are up/down counters constructed with

MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. The

counter consists of type D flip−flop stages with a gating structure to provide type T flip−flop capability.

The counter can be cleared by applying a high level on the Reset line. These complementary MOS

counters find primary use in up/down and difference counting and frequency synthesizer applications

where low power and/or high noise immunity is desired. They are also useful in A/D and D/A conversion

for magnitude and sign generation.

Features:

D Noise Immunity = 45% of V_DD(Typ)

D Diode Protection on All Inputs

D Supply Voltage Range = 3Vdc to 10Vdc

D Low Input Capacitance = 5pF (Typ)

D Internally Synchronous for High Speed

D Logic Edge−Clocked Design − Count Occurs on Positive Going Edge of Clock

D 5Mhz Counting Rate

D Asynchronous Preset Enable Operation

D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two

HTL Loads Over the Rated Temperature Range

Absolute Maximum Ratings: (Voltages Referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (All Inputs), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DD+ 0.5V

DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Operating Temperature Range, T_A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C

Storage Temperature Range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C

Note 1. These devices contain circuitry to protect the inputs against damage due to high static

voltages or electric fields; however, it is advised that normal precautions be taken to avoid

application of any voltage higher than maximum rated voltages to this high impedance cir-

cuit. For proper operation is is recommended that V_inand V_outbe constrained to the range

V_SS≤ (V_inor V_out) ≤ V_DD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V_SSor

V_DD).

12 3 4 5

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