Datasheet > NTE4077BT

NTE4077BT

更新时间： 2024-11-03 21:05:35

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NTE4077BT 技术参数

NTE4077B and NTE4077BT

Integrated Circuit

CMOS, Quad Exclusive NOR Gate

Description:

The NTE4077B (14−Lead DIP) and NTE4077BT (SOIC−14) are quad exclusive NOR gates

constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use where low power dissipation and/

or high noise immunity is desired.

Features:

D Quiescent Current = 0.5nA Typ/Pkg at 5 Vdc

D Noise Immunity = 45% of V_DD(Typ)

D Supply Voltage Range = 3Vdc to 18Vdc

D All Outputs Buffered

D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two

HTL Loads Over the Rated Temperature Range

D Double Diode Protection on All Inputs

Absolute Maximum Ratings: (Voltages Referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (All Inputs), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DD+ 0.5V

DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Operating Temperature Range, T_sA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C

Storage Temperature Range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C

Lead Temperature (8−Seconds Soldering), T_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Note 1. These devices contain circuitry to protect the inputs against damage due to high static

voltages or electric fields; however, it is advised that normal precautions be taken to avoid

application of any voltage higher than maximum rated voltages to this high impedance cir-

cuit. For proper operation is is recommended that V_inand V_outbe constrained to the range

V_SS≤ (V_inor V_out) ≤ V_DD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V_SSor

V_DD).

12 3 4

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