Datasheet > NTE4073BT

NTE4073BT

更新时间： 2024-11-03 19:43:51

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NTE4073BT 技术参数

NTE4073B & NTE4073BT

Integrated Circuit

CMOS, Triple 3−Input AND Gate

Description:

The NTE4073B (14−Lead DIP) and NTE4073BT (SOIC−14) are triple 3−input AND gate devices

constructed with P−Channel and N−Channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use where low power dissipation

and/or high noise immunity is desired.

Features:

D Supply Voltage Range: 3Vdc to 18Vdc

D All Outputs Buffered

D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over

the Rated Temperature Range

D Double Diode Protection on All Inputs

Absolute Maximum Ratings: (Voltages referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (DC or Transient), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Output Voltage (DC or Transient), V_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Input Current (DC or Transient, Per Pin), I_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Output Current (DC or Transient, Per Pin), I_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation (Per Package), P_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Temperature Derating (from +65° to +125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7.0mW/°C

Storage Temperature, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C

Lead Temperature (During Soldering, 8sec max), T_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Note 1. Maximum Ratings are those values beyond which damage to the device may occur.

12 3 4

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