NTD4963N
Power MOSFET
30 V, 44 A, Single N−Channel, DPAK/IPAK
Features
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
V
R
MAX
I
D
MAX
(BR)DSS
DS(ON)
9.6 mW @ 10 V
16 mW @ 4.5 V
30 V
Applications
44 A
• CPU Power Delivery
• DC−DC Converters
• Recommended for High Side (Control)
D
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
30
Unit
G
V
DSS
V
V
A
V
GS
20
S
Continuous Drain
Current R
I
D
T = 25°C
10.0
N−CHANNEL MOSFET
A
q
JA
T = 85°C
A
7.2
(Note 1)
Power Dissipation
(Note 1)
4
4
T = 25°C
A
P
D
1.64
W
A
4
R
q
JA
Continuous Drain
Current R
ID
T = 25°C
A
8.1
5.8
1.1
q
JA
2
1
1
T = 85°C
A
Steady
State
(Note 2)
1
2
3
3
2
3
Power Dissipation
T = 25°C
A
P
I
W
A
D
CASE 369AC
3 IPAK
(Straight Lead)
R
(Note 2)
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
CASE 369D
IPAK
(Straight Lead
DPAK)
q
JA
Continuous Drain
Current R
T
C
T
C
T
C
= 25°C
= 85°C
= 25°C
44
32
D
q
JC
(Note 1)
Power Dissipation
(Note 1)
P
D
35.7
W
A
R
q
MARKING DIAGRAMS
& PIN ASSIGNMENTS
JC
Pulsed Drain
Current
t =10ms
p
T = 25°C
A
I
DM
132
35
4
Drain
Current Limited by Package
T = 25°C
A
I
A
DmaxPkg
4
4
Drain
Drain
Operating Junction and Storage
Temperature
T ,
−55 to
+175
°C
J
T
STG
Source Current (Body Diode)
Drain to Source dV/dt
I
30
6.0
A
S
dV/dt
EAS
V/ns
mJ
Single Pulse Drain−to−Source Avalanche
Energy (T = 25°C, V = 50 V, V = 10 V,
33.8
J
DD
GS
2
1
2
3
I = 26 A , L = 0.1 mH, R = 25 W)
L
pk
G
Drain
1
3
Gate Drain Source
Gate Source
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
T
L
260
°C
1
2
3
Gate Drain Source
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Y
WW
= Year
= Work Week
4963N = Device Code
= Pb−Free Package
G
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
December, 2009 − Rev. 0
NTD4963N/D