Datasheet > NT80960JT-100

NT80960JT-100

更新时间： 2024-09-18 05:24:03

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
86页	4874K
描述
RISC Microprocessor, 32-Bit, 100MHz, CMOS, PQFP132

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数据手册

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NT80960JT-100 数据手册

80960JA/JF/JD/JS/JC/JT 3.3 V

Embedded 32-Bit Microprocessor

Datasheet

Product Features

■ Code Compatible with all 80960Jx

■ On-Chip Data RAM

Processors

—1 Kbyte Critical Variable Storage

—Single-Cycle Access

■ High-Performance Embedded Architecture

—One Instruction/Clock Execution

■ 3.3 V Supply Voltage

—Core Clock Rate is:

—5 V Tolerant Inputs

1x the Bus Clock for 80960JA/JF/JS

2x the Bus Clock for 80960JD/JC

3x the Bus Clock for 80960JT

—TTL Compatible Outputs

■ High Bandwidth Burst Bus

—32-Bit Multiplexed Address/Data

—Programmable Memory Configuration

—Selectable 8-, 16-, 32-Bit Bus Widths

—Supports Unaligned Accesses

—Big or Little Endian Byte Ordering

■ High-Speed Interrupt Controller

—31 Programmable Priorities

—Eight Maskable Pins plus NMI#

—Up to 240 Vectors in Expanded Mode

■ Two On-Chip Timers

—Load/Store Programming Model

—Sixteen 32-Bit Global Registers

—Sixteen 32-Bit Local Registers (8 sets)

—Nine Addressing Modes

—User/Supervisor Protection Model

■ Two-Way Set Associative Instruction

Cache

—80960JA - 2 Kbyte

—80960JF/JD - 4 Kbyte

—80960JS/JC/JT - 16 Kbyte

—Programmable Cache-Locking

Mechanism

—Independent 32-Bit Counting

—Clock Prescaling by 1, 2, 4 or 8

—Internal Interrupt Sources

■ Direct Mapped Data Cache

—80960JA - 1 Kbyte

■ Halt Mode for Low Power

■ IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

■ Packages

—80960JF/JD - 2 Kbyte

—80960JS/JC/JT - 4 Kbyte

—Write Through Operation

■ On-Chip Stack Frame Cache

—Seven Register Sets May Be Saved

—Automatic Allocation on Call/Return

—132-Lead Pin Grid Array (PGA)

—132-Lead Plastic Quad Flat Pack

(PQFP)

—196-Ball Mini Plastic Ball Grid Array

(MPBGA)

—0-7 Frames Reserved for High-Priority

Interrupts

Order Number: 273159-006

August 2004

12 3 4 5 6 7...86

中文翻译

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