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NSI6602VA-DLAR PDF预览

NSI6602VA-DLAR

更新时间: 2024-11-19 17:00:15
品牌 Logo 应用领域
纳芯微 - NOVOSENSE 开关栅极驱动晶体管驱动器
页数 文件大小 规格书
32页 1560K
描述
NSI6602V是纳芯微第二代高可靠性的隔离式双通道栅极驱动器IC, 增强了抗干扰能力和驱动能力,且功耗更低,同时提高了输入侧的耐压能力。可以驱动高达2MHz开关频率的功率晶体管。每个通道输出可以

NSI6602VA-DLAR 数据手册

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NSI6602V  
High Reliability Isolated Dual-Channel  
Gate Driver  
Datasheet (EN) 1.1  
Product Overview  
Safety Regulatory Approvals  
NSI6602V is a family of high reliability isolated dual-  
channel gate driver ICs which can be designed to drive  
power transistor up to 2MHz switching frequency. Each  
output could source 6A and sink 8A peak current with  
fast 33ns propagation delay and 6ns maximum delay  
matching.  
UL recognition:  
LGA13 (4x4mm): 1600Vrms for 1 minute per UL1577  
LGA13 (5x5mm): 2500Vrms for 1 minute per UL1577  
SOW16/SOW14: 5700Vrms for 1 minute per UL1577  
SOP16: 3000Vrms for 1 minute per UL1577  
The NSI6602V provides 1600Vrms isolation per UL1577 in  
4-mm x 4-mm LGA13 package, 2500Vrms isolation per  
UL1577 in 5-mm x 5-mm LGA13 package, 3000Vrms  
isolation in SOP16 package, and 5700Vrms isolation in  
SOW16 or SOW14 package. System robustness is  
supported by 150kV/us typical common-mode transient  
immunity (CMTI).  
DIN EN IEC 60747-17 (VDE 0884-17)  
CSA component notice 5A  
CQC certification per GB4943.  
Applications  
The driver operates with a maximum supply voltage of  
25V, while the input-side accepts from 3V to 18V supply  
voltage. Under voltage lock-out (UVLO) protection is  
supported by all the power supply voltage pins.  
Isolated DC-DC and AC-to-DC power supplies in server,  
telecom, and industry  
DC-to-AC solar inverters  
Motor drives and EV charging  
UPS and battery chargers  
Key Features  
Functional Block Diagram  
Isolated dual channel driver  
Input side supply voltage: 3V to 18V  
Driver side supply voltage: up to 25V with UVLO  
6A peak source and 8A peak sink output  
High CMTI: 150kV/us typical  
VDDI  
VDDA  
OUTA  
GNDA  
MOD  
DEMOD  
UVLO  
INA  
DT  
UVLO,  
Disable  
&
Functional Isolation  
Dead-  
Time  
DIS  
INB  
VDDB  
OUTB  
GNDB  
33ns typical propagation delay  
MOD  
DEMOD  
UVLO  
GNDI  
6ns maximum delay matching  
8ns maximum pulse width distortion  
Programmable deadtime  
Figure 0.1 NSI6602V Block Diagram  
Accepts minimum input pulse width 20ns  
Operation temperature: -40~125℃  
RoHS & REACH Compliant  
Copyright © 2023, NOVOSENSE  
Page 1  

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