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MM82PC12VI/A+ PDF预览

MM82PC12VI/A+

更新时间: 2024-02-24 14:27:20
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
8页 182K
描述
IC,I/O PORT,8-BIT,CMOS,LDCC,28PIN,PLASTIC

MM82PC12VI/A+ 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
位数:8端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
子类别:Parallel IO Port标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

MM82PC12VI/A+ 数据手册

 浏览型号MM82PC12VI/A+的Datasheet PDF文件第2页浏览型号MM82PC12VI/A+的Datasheet PDF文件第3页浏览型号MM82PC12VI/A+的Datasheet PDF文件第4页浏览型号MM82PC12VI/A+的Datasheet PDF文件第5页浏览型号MM82PC12VI/A+的Datasheet PDF文件第6页浏览型号MM82PC12VI/A+的Datasheet PDF文件第7页 
July 1987  
MM82PC12 8-Bit Input/Output Port  
General Description  
Features  
Y
Y
Y
Y
Y
Y
Y
Y
Drive capabilityÐ150 pF load  
The MM82PC12 is a microCMOS 8-bit input/output port  
contained in a standard 24-pin dual-in-line package. The  
MM82PC12 can be used to implement latches, gated buff-  
ers, or multiplexers. Thus, all of the major peripheral and  
input/output functions of a microcomputer system can be  
implemented with this device.  
High noise immunity  
Low power dissipation  
Full interface to CMOS logic levels  
microCMOS technology  
e
TTL drive capability when V  
8-bit data latch and buffer  
5V  
CC  
The MM82PC12 includes an 8-bit latch with TRI-STATE  
É
output buffers, and device selection and control logic. Also  
included is a service request flip-flop for the generation and  
control of interrupts to the microprocessor.  
Service request flip-flop for generation and control of  
interrupts  
Y
Y
1 mA input load current  
The MM82PC12 is pinout and function compatible with stan-  
dard INS8212 and DP8212 devices.  
Reduces system package count by replacing buffers,  
latches, and multiplexers in microcomputer systems  
For military applications, the MM82PC12 is available with  
class B screening in accordance with method 5004 of MIL-  
STD-883.  
System Configuration  
TL/C/5596–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/C/5596  
RRD-B30M105/Printed in U. S. A.  

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