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LF398A

更新时间: 2024-01-27 22:35:31
品牌 Logo 应用领域
美国国家半导体 - NSC 采样保持电路
页数 文件大小 规格书
13页 523K
描述
Monolithic Sample-and-Hold Circuits

LF398A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.64
最长采集时间:6 µs放大器类型:SAMPLE AND HOLD CIRCUIT
JESD-30 代码:R-PDSO-GJESD-609代码:e0
功能数量:1封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
采样并保持/跟踪并保持:SAMPLE子类别:Sample and Hold Circuit
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

LF398A 数据手册

 浏览型号LF398A的Datasheet PDF文件第2页浏览型号LF398A的Datasheet PDF文件第3页浏览型号LF398A的Datasheet PDF文件第4页浏览型号LF398A的Datasheet PDF文件第5页浏览型号LF398A的Datasheet PDF文件第6页浏览型号LF398A的Datasheet PDF文件第7页 
July 2000  
LF198/LF298/LF398, LF198A/LF398A  
Monolithic Sample-and-Hold Circuits  
General Description  
Features  
±
±
n Operates from 5V to 18V supplies  
n Less than 10 µs acquisition time  
n TTL, PMOS, CMOS compatible logic input  
n 0.5 mV typical hold step at Ch = 0.01 µF  
n Low input offset  
The LF198/LF298/LF398 are monolithic sample-and-hold  
circuits which utilize BI-FET technology to obtain ultra-high  
dc accuracy with fast acquisition of signal and low droop  
rate. Operating as a unity gain follower, dc gain accuracy is  
0.002% typical and acquisition time is as low as 6 µs to  
0.01%. A bipolar input stage is used to achieve low offset  
voltage and wide bandwidth. Input offset adjust is accom-  
plished with a single pin, and does not degrade input offset  
drift. The wide bandwidth allows the LF198 to be included in-  
side the feedback loop of 1 MHz op amps without having sta-  
bility problems. Input impedance of 1010allows high  
source impedances to be used without degrading accuracy.  
n 0.002% gain accuracy  
n Low output noise in hold mode  
n Input characteristics do not change during hold mode  
n High supply rejection ratio in sample or hold  
n Wide bandwidth  
n Space qualified, JM38510  
P-channel junction FET’s are combined with bipolar devices  
in the output amplifier to give droop rates as low as 5 mV/min  
with a 1 µF hold capacitor. The JFET’s have much lower  
noise than MOS devices used in previous designs and do  
not exhibit high temperature instabilities. The overall design  
guarantees no feed-through from input to output in the hold  
mode, even for input signals equal to the supply voltages.  
Logic inputs on the LF198 are fully differential with low input  
current, allowing direct connection to TTL, PMOS, and  
CMOS. Differential threshold is 1.4V. The LF198 will operate  
±
±
from 5V to 18V supplies.  
An “A” version is available with tightened electrical  
specifications.  
Typical Connection and Performance Curve  
Acquisition Time  
DS005692-32  
DS005692-16  
Functional Diagram  
DS005692-1  
© 2000 National Semiconductor Corporation  
DS005692  
www.national.com  

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