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DP83865 PDF预览

DP83865

更新时间: 2024-01-24 12:02:59
品牌 Logo 应用领域
美国国家半导体 - NSC 以太网局域网(LAN)标准
页数 文件大小 规格书
86页 589K
描述
DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer

DP83865 技术参数

生命周期:Not Recommended零件包装代码:QFP
包装说明:FQFP, QFP128,.67X.93,20针数:128
Reach Compliance Code:not_compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.98Samacsys Confidence:3
Samacsys Status:Released2D Presentation:https://componentsearchengine.com/2D/0T/154556.1.1.png
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=154556PCB Footprint:https://componentsearchengine.com/footprint.php?partID=154556
3D View:https://componentsearchengine.com/viewer/3D.php?partID=154556Samacsys PartID:154556
Samacsys Image:https://componentsearchengine.com/Images/9/DP83865DVH.jpgSamacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/DP83865DVH.jpg
Samacsys Pin Count:128Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Quad Flat PackagesSamacsys Footprint Name:VLA128A
Samacsys Released Date:2015-05-24 21:47:42Is Samacsys:N
数据速率:1000000 MbpsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
湿度敏感等级:3功能数量:1
端子数量:128收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP128,.67X.93,20封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):245
电源:1.8,2.5/3.3 V认证状态:Not Qualified
座面最大高度:3.15 mm子类别:Network Interfaces
标称供电电压:1.8 V表面贴装:YES
技术:CMOS电信集成电路类型:INTERFACE CIRCUIT
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

DP83865 数据手册

 浏览型号DP83865的Datasheet PDF文件第2页浏览型号DP83865的Datasheet PDF文件第3页浏览型号DP83865的Datasheet PDF文件第4页浏览型号DP83865的Datasheet PDF文件第5页浏览型号DP83865的Datasheet PDF文件第6页浏览型号DP83865的Datasheet PDF文件第7页 
October 2004  
DP83865 Gig PHYTER® V  
10/100/1000 Ethernet Physical Layer  
General Description  
The DP83865 is a fully featured Physical Layer transceiver  
with integrated PMD sublayers to support 10BASE-T,  
100BASE-TX and 1000BASE-T Ethernet protocols.  
Integrated PMD sublayer featuring adaptive equalization  
and baseline wander compensation according to ANSI  
X3.T12  
The DP83865 is an ultra low power version of the DP83861  
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS  
technology, fabricated at National Semiconductor’s South  
Portland, Maine facility.  
3.3 V or 2.5 V MAC interfaces:  
IEEE 802.3u MII  
IEEE 802.3z GMII  
The DP83865 is designed for easy implementation of  
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to  
Twisted Pair media via an external transformer. This device  
interfaces directly to the MAC layer through the IEEE  
802.3u Standard Media Independent Interface (MII), the  
IEEE 802.3z Gigabit Media Independent Interface (GMII),  
or Reduced GMII (RGMII).  
RGMII version 1.3  
User programmable GMII pin ordering  
IEEE 802.3u Auto-Negotiation and Parallel Detection  
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,  
The DP83865 is a fourth generation Gigabit PHY with field  
proven architecture and performance. Its robust perfor-  
mance ensures drop-in replacement of existing  
10/100 Mbps equipment with ten to one hundred times the  
performance using the existing networking infrastructure.  
and 10 Mb/s full duplex and half duplex devices  
Speed Fallback mode to achieve quality link  
Cable length estimator  
LED support for activity, full / half duplex, link1000,  
link100 and link10, user programmable (manual on/off),  
or reduced LED mode  
Applications  
The DP83865 fits applications in:  
10/100/1000 Mb/s capable node cards  
Switches with 10/100/1000 Mb/s capable ports  
High speed uplink ports (backbone)  
Supports 25 MHz operation with crystal or oscillator.  
Requires only two power supplies, 1.8 V (core and  
analog) and 2.5 V (analog and I/O). 3.3V is supported  
as an alternative supply for I/O voltage  
Features  
User programable interrupt  
Ultra low power consumption typically 1.1 watt  
Supports Auto-MDIX at 10, 100 and 1000 Mb/s  
Supports JTAG (IEEE1149.1)  
Fully compliant with IEEE 802.3 10BASE-T, 100BASE-  
TX and 1000BASE-T specifications  
128-pin PQFP package (14mm x 20mm)  
SYSTEM DIAGRAM  
MII  
GMII  
RGMII  
10BASE-T  
100BASE-TX  
1000BASE-T  
DP83820  
10/100/1000 Mb/s  
ETHERNET MAC  
DP83865  
10/100/1000 Mb/s  
ETHERNET PHYSICAL LAYER  
25 MHz  
crystal or oscillator  
STATUS  
LEDs  
PHYTER® is a registered trademark of National Semiconductor Corporation  
© 2004 National Semiconductor Corporation  
www.national.com  

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