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DP8344V

更新时间: 2024-02-04 08:20:31
品牌 Logo 应用领域
美国国家半导体 - NSC 通信
页数 文件大小 规格书
184页 2218K
描述
IC,COMMUNICATIONS CONTROLLER,CMOS,LDCC,84PIN

DP8344V 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC84,1.2SQReach Compliance Code:unknown
风险等级:5.86JESD-30 代码:S-PQCC-J84
JESD-609代码:e0端子数量:84
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
认证状态:Not Qualified子类别:Other Microprocessor ICs
标称供电电压:5 V表面贴装:YES
技术:CMOS端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

DP8344V 数据手册

 浏览型号DP8344V的Datasheet PDF文件第2页浏览型号DP8344V的Datasheet PDF文件第3页浏览型号DP8344V的Datasheet PDF文件第4页浏览型号DP8344V的Datasheet PDF文件第5页浏览型号DP8344V的Datasheet PDF文件第6页浏览型号DP8344V的Datasheet PDF文件第7页 
November 1991  
DP8344B Biphase Communications ProcessorÐBCP  
although a TTL-level serial input is also provided for applica-  
É
General Description  
The DP8344B BCP is a communications processor de-  
tions where an external comparator is preferred.  
A typical system is shown below. Both coax and twinax line  
interfaces are shown, as well as an example of the (option-  
al) remote processor interface.  
signed to efficiently process IBM 3270, 3299 and 5250  
É
communications protocols. A general purpose 8-bit protocol  
is also supported.  
The BCP integrates a 20 MHz 8-bit Harvard architecture  
RISC processor, and an intelligent, software-configurable  
transceiver on the same low power microCMOS chip. The  
transceiver is capable of operating without significant proc-  
essor interaction, releasing processor power for other tasks.  
Fast and flexible interrupt and subroutine capabilities with  
on-chip stacks make this power readily available.  
Features  
Transceiver  
Y
Software configurable for 3270, 3299, 5250 and general  
8-bit protocols  
Y
Fully registered status and control  
Y
On-chip analog line receiver  
Processor  
The transceiver is mapped into the processor’s register  
space, communicating with the processor via an asynchro-  
nous interface which enables both sections of the chip to  
run from different clock sources. The transmitter and receiv-  
er run at the same basic clock frequency although the re-  
ceiver extracts a clock from the incoming data stream to  
ensure timing accuracy.  
Y
20 MHz clock (50 ns T-states)  
Y
Max. instruction cycle: 200 ns  
Y
33 instruction types (50 total opcodes)  
Y
ALU and barrel shifter  
Y
64k x 8 data memory address range  
Y
64k x 16 program memory address range  
k
(note: typical system requires 2k program memory)  
The BCP is designed to stand alone and is capable of imple-  
menting a complete communications interface, using the  
processor’s spare power to control the complete system.  
Alternatively, the BCP can be interfaced to another proces-  
sor with an on-chip interface controller arbitrating access to  
data memory. Access to program memory is also possible,  
providing the ability to download BCP code.  
Y
Y
Y
Y
Y
Programmable wait states  
Soft-loadable program memory  
Interrupt and subroutine capability  
Stand alone or host operation  
Flexible bus interface with on-chip arbitration logic  
A simple line interface connects the BCP to the communica-  
tions line. The receiver includes an on-chip analog compar-  
ator, suitable for use in a transformer-coupled environment,  
General  
Y
e
84-pin plastic leaded chip carrier (PLCC) package  
Low power microCMOS; typ. I  
25 mA at 20 MHz  
CC  
Y
Block Diagram  
Typical BCP System  
TL/F/933651  
FIGURE 1  
BCPÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.  
IBMÉ is a registered trademark of International Business Machines Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9336  
RRD-B30M105/Printed in U. S. A.  

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