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74F189PCQR PDF预览

74F189PCQR

更新时间: 2024-02-05 11:00:37
品牌 Logo 应用领域
美国国家半导体 - NSC 存储
页数 文件大小 规格书
8页 169K
描述
IC,SRAM,16X4,F-TTL,DIP,16PIN,PLASTIC

74F189PCQR 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.76
最长访问时间:20 nsJESD-30 代码:R-PDIP-T16
内存密度:64 bit内存集成电路类型:STANDARD SRAM
内存宽度:4功能数量:1
端子数量:16字数:16 words
字数代码:16工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16X4封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

74F189PCQR 数据手册

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August 1995  
54F/74F189 64-Bit Random Access  
Memory with TRI-STATE Outputs  
É
General Description  
Features  
Y
TRI-STATE outputs for data bus applications  
Buffered inputs minimize loading  
Address decoding on-chip  
The ’F189 is a high-speed 64-bit RAM organized as a 16-  
word by 4-bit array. Address inputs are buffered to minimize  
loading and are fully decoded on-chip. The outputs are TRI-  
STATE and are in the high impedance state whenever the  
Chip Select (CS) input is HIGH. The outputs are active only  
in the Read mode and the output data is the complement of  
the stored data.  
Y
Y
Y
Y
Diode clamped inputs minimize ringing  
Available in SOIC, (300 mil only)  
Package  
Commercial  
74F189PC  
Military  
Package Description  
Number  
N16E  
J16A  
16-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F189DL (Note 2)  
16-Lead Ceramic Dual-In-Line  
74F189SC (Note 1)  
74F189SJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
16-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F189FL (Note 2)  
54F189LL (Note 2)  
16-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DLQB, FLQB and LLQB.  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/9493–1  
IEEE/IEC  
TL/F/9493–2  
TL/F/9493–3  
TL/F/9493–4  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9493  
RRD-B30M105/Printed in U. S. A.  

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