74191

更新时间： 2024-02-27 20:49:46

品牌	Logo	应用领域
美国国家半导体 - NSC		计数器
页数	文件大小	规格书
6页	132K
描述
Synchronous Up/Down 4-Bit Binary Counter with Mode Control

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技术参数
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74191 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	DIP, DIP16,.3
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.88	计数方向：	BIDIRECTIONAL
JESD-30 代码：	R-PDIP-T16	JESD-609代码：	e0
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	湿度敏感等级：	2A
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	250
电源：	5 V	子类别：	Counters
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

74191 数据手册

June 1989

54191/DM54191/DM74191 Synchronous Up/Down

4-Bit Binary Counter with Mode Control

General Description

This circuit is a synchronous, reversible, up/down counter.

The 191 is a 4-bit binary counter. Synchronous operation is

provided by having all flip-flops clocked simultaneously so

that the outputs change simultaneously when so instructed

by the steering logic. This mode of operation eliminates the

output counting spikes normally associated with asynchro-

nous (ripple clock) counters.

Two outputs have been made available to perform the cas-

cading function: ripple clock and maximum/minimum count.

The latter output produces a high-level output pulse with a

duration approximately equal to one complete cycle of the

clock when the counter overflows or underflows. The ripple

clock output produces a low-level output pulse equal in

width to the low-level portion of the clock input when an

overflow or underflow condition exists. The counters can be

easily cascaded by feeding the ripple clock output to the

enable input of the succeeding counter if parallel clocking is

used, or to the clock input if parallel enabling is used. The

maximum/minimum count output can be used to accom-

plish look-ahead for high-speed operation.

The outputs of the four master-slave flip-flops are triggered

on a low-to-high level transition of the clock input, if the

enable input is low. A high at the enable input inhibits count-

ing. Level changes at either the enable input or the down/

up input should be made only when the clock input is high.

The direction of the count is determined by the level of the

down/up input. When low, the counter counts up and when

high, it counts down.

Features

Single down/up count control line

This counter is fully programmable; that is, the outputs may

be preset to either level by placing a low on the load input

and entering the desired data at the data inputs. The output

will change independent of the level of the clock input. This

feature allows the counters to be used as modulo-N dividers

by simply modifying the count length with the preset inputs.

Count enable control input

Ripple clock output for cascading

Asynchronously presettable with load control

Parallel outputs

Cascadable for n-bit applications

The clock, down/up, and load inputs are buffered to lower

the drive requirement; which significantly reduces the num-

ber of clock drivers, etc., required for long parallel words.

Alternate Military/Aerospace device (54191) is avail-

able. Contact a National Semiconductor Sales Office/

Distributor for specifications.

Connection Diagram

Dual-In-Line Package

TL/F/6562–1

Order Number 54191DMQB, 54191FMQB,

DM54191J, DM54191W or DM74191N

See NS Package Number J16A, N16E or W16A

1995 National Semiconductor Corporation

TL/F/6562

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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74191B	NXP	IC TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16,	获取价格

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