5秒后页面跳转
54LS256 PDF预览

54LS256

更新时间: 2024-01-30 14:01:46
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
6页 129K
描述
Dual 4-Bit Addressable Latch

54LS256 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.9
JESD-30 代码:R-XDFP-F16JESD-609代码:e0
逻辑集成电路类型:D LATCH位数:4
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

54LS256 数据手册

 浏览型号54LS256的Datasheet PDF文件第2页浏览型号54LS256的Datasheet PDF文件第3页浏览型号54LS256的Datasheet PDF文件第4页浏览型号54LS256的Datasheet PDF文件第5页浏览型号54LS256的Datasheet PDF文件第6页 
June 1989  
54LS256/DM74LS256  
Dual 4-Bit Addressable Latch  
General Description  
The ’LS256 is a dual 4-bit addressable latch with common  
control inputs; these include two Address inputs (A0, A1),  
an active LOW enable input (E) and an active LOW Clear  
input (CL). Each latch has a Data input (D) and four outputs  
(Q0Q3).  
could impose a transient wrong address. Therefore, this  
e
CL  
e
should be done only while in the memory mode (E  
HIGH).  
Features  
Y
When the Enable (E) is HIGH and the Clear input (CL) is  
LOW, all outputs (Q0Q3) are LOW. Dual 4-channel demul-  
tiplexing occurs when the CL and E are both LOW. When  
CL is HIGH and E is LOW, the selected output (Q0Q3),  
determined by the Address inputs, follows D. When the E  
goes HIGH, the contents of the latch are stored. When op-  
Serial-to-parallel capability  
Y
Output from each storage bit available  
Y
Random (addressable) data entry  
Y
Easily expandable  
Y
Active low common clear  
e
e
LOW, CL  
erating in the addressable latch mode (E  
HIGH), changing more than one bit of the Address (A0, A1)  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/9823–1  
TL/F/9823–2  
Order Number 54LS256DMQB,  
54LS256FMQB or DM74LS256N  
See NS Package Number J16A,  
N16E or W16A  
e
e
V
Pin 16  
CC  
GND  
Pin 8  
Pin Names  
A0, A1  
Description  
Common Address Inputs  
Data Inputs  
D , D  
a
b
E
Common Enable Input (Active LOW)  
Conditional Clear Input (Active LOW)  
Side A Latch Outputs  
CL  
Q0 Q a  
3
a
Q0 Q b  
b 3  
Side B Latch Outputs  
C
1995 National Semiconductor Corporation  
TL/F/9823  
RRD-B30M115/Printed in U. S. A.  

与54LS256相关器件

型号 品牌 描述 获取价格 数据表
54LS256/BEBJC MOTOROLA D Latch, 2-Func, 4-Bit, TTL, CDIP16

获取价格

54LS256DM NSC IC,LATCH,DUAL,4-BIT,LS-TTL,DIP,16PIN,CERAMIC

获取价格

54LS256DMQB NSC Dual 4-Bit Addressable Latch

获取价格

54LS256FMQB NSC Dual 4-Bit Addressable Latch

获取价格

54LS257 MOTOROLA QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS

获取价格

54LS257 NSC TRI-STATE Quad 2-Data Selectors/Multiplexers

获取价格