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54FCT377LMQB PDF预览

54FCT377LMQB

更新时间: 2024-01-16 03:10:44
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器时钟
页数 文件大小 规格书
8页 155K
描述
Octal D-Type Flip-Flop with Clock Enable

54FCT377LMQB 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.75
Is Samacsys:NBase Number Matches:1

54FCT377LMQB 数据手册

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October 1999  
54FCT377  
Octal D-Type Flip-Flop with Clock Enable  
General Description  
Features  
n Clock enable for address and data synchronization  
applications  
The ’FCT377 has eight edge-triggered, D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) input loads all flip-flops simultaneously, when the  
Clock Enable (CE) is LOW.  
n Eight edge-triggered D flip-flops  
n Buffered common clock  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to the  
LOW-to-HIGH clock transition for predictable operation.  
n See ’FCT273 for master reset version  
n See ’FCT373 for transparent latch version  
n See ’FCT374 for TRI-STATE® version  
n TTL input and output level compatible  
n CMOS power consumption  
n Output sink capability of 32 mA, source capability of  
12 mA  
n Standard Microcircuit Drawing (SMD) 5962-8762701  
Ordering Code  
Military  
Package  
Number  
Package Description  
54FCT377DMQB  
J20A  
20-Lead Ceramic Dual-In-Line  
20-Lead Cerpack  
54FCT377FMQB  
54FCT377LMQB  
W20A  
E20A  
20-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagram  
Pin Assignment for LCC  
Pin Assignment for  
DIP and Cerpack  
DS100952-11  
Pin  
Description  
DS100952-1  
Names  
D0–D7 Data Inputs  
CE  
CP  
Clock Enable (Active LOW)  
Clock Pulse Input  
Q0–Q7 Data Outputs  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS100952  
www.national.com  

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