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54FCT273DMQB PDF预览

54FCT273DMQB

更新时间: 2024-02-10 04:29:23
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 148K
描述
Octal D-Type Flip-Flop

54FCT273DMQB 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.92
Is Samacsys:NJESD-30 代码:S-XQCC-N20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.048 A
功能数量:8端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
电源:5 V认证状态:Not Qualified
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
Base Number Matches:1

54FCT273DMQB 数据手册

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August 1998  
54FCT273  
Octal D-Type Flip-Flop  
General Description  
Features  
n Eight edge-triggered D flip-flops  
n Buffered common clock  
The ’FCT273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
n Buffered, asynchronous Master Reset  
n See ’FCT377 for clock enable version  
n See ’FCT373 for transparent latch version  
n See ’FCT374 for TRI-STATE® version  
n Output sink capability of 32 mA, source capability of  
12 mA  
n TTL input and output level compatible  
n CMOS power consumption  
n Standard Microcircuit Drawing (SMD) 5962-8765601  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The de-  
vice is useful for applications where the true output only is re-  
quired and the Clock and Master Reset are common to all  
storage elements.  
Ordering Code  
Military  
Package  
Number  
Package Description  
54FCT273DMQB  
54FCT273FMQB  
54FCT273LMQB  
J20A  
20-Lead Ceramic Dual-In-Line  
20-Lead Cerpack  
W20A  
E20A  
20-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagrams  
Pin Assignment for DIP  
and Flatpack  
Pin Assignment  
for LCC  
DS100956-2  
DS100956-1  
Pin  
Names  
D0–D7  
MR  
Description  
Data Inputs  
Master Reset  
(Active LOW)  
CP  
Clock Pulse Input  
(Active Rising Edge)  
Data Outputs  
Q0–Q7  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100956  
www.national.com  

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