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54ACTQ533D PDF预览

54ACTQ533D

更新时间: 2024-01-07 10:01:41
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
8页 159K
描述
Quiet Series Octal Transparent Latch with TRI-STATE Outputs

54ACTQ533D 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
系列:ACTJESD-30 代码:S-CQCC-N20
JESD-609代码:e0长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):10.5 ns认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:1.905 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

54ACTQ533D 数据手册

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August 1998  
54ACTQ533  
Quiet Series Octal Transparent Latch with TRI-STATE®  
Outputs  
General Description  
Features  
n ICC and IOZ reduced by 50%  
The ACTQ533 consists of eight latches with TRI-STATE out-  
puts for bus organized system applications. The flip-flops ap-  
pear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is low, the data satisfying the input timing re-  
quirements is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the bus out-  
put is in the high impedance state.  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
n Improved latch up immunity  
n Eight latches in a single package  
n TRI-STATE outputs drive bus lines or buffer memory  
address registers  
The ACTQ533 utilizes NSC Quiet Series technology to guar-  
antee quiet output switching and improve dynamic threshold  
n Outputs source/sink 24 mA  
n Inverted version of the ACTQ373  
n 4 kV minimum ESD immunity  
performance. FACT Quiet Series features GTO output  
control and undershoot corrector in addition to a split ground  
bus for superior performance.  
Logic Symbols  
IEEE/IEC  
DS100241-1  
DS100241-2  
Pin  
Description  
Names  
D0–D7  
LE  
Data Inputs  
Latch Enable Input  
OE  
Output Enable Input  
O0–O7  
TRI-STATE Latch  
Outputs  
GTO is a trademark of National Semiconductor Corporation.  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100241  
www.national.com  

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