54ACT715

更新时间： 2024-01-17 20:56:28

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
16页	343K
描述
Programmable Video Sync Generator

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

54ACT715 技术参数

生命周期：	Obsolete	包装说明：	DIP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.59	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDIP-T20
长度：	24.892 mm	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大压摆率：	1.6 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
表面贴装：	NO	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	7.62 mm
Base Number Matches：	1

54ACT715 数据手册

December 1998

LM1882•54ACT715

LM1882-R•54ACT715-R Programmable Video Sync

Generator

LM1882-R is mask programmed to default to a Clock En-

abled state. Bit 10 of the Status Register defaults to a logic

General Description

The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin

“1”. Although completely (re)programmable, the ’ACT715-R/

TTL-input compatible devices capable of generating Hori-

LM1882-R version is better suited for applications using the

zontal, Vertical and Composite Sync and Blank signals for

default 14.31818 MHz RS-170 register values. This feature

televisions and monitors. All pulse widths are completely de-

allows power-up directly into operation, following a single

finable by the user. The devices are capable of generating

CLEAR pulse.

signals for both interlaced and noninterlaced modes of op-

eration. Equalization and serration pulses can be introduced

into the Composite Sync signal when needed.

Features

n Maximum Input Clock Frequency 130 MHz

Four additional signals can also be made available when

Composite Sync or Blank are used. These signals can be

used to generate horizontal or vertical gating pulses, cursor

position or vertical Interrupt signal.

n Interlaced and non-interlaced formats available

n Separate or composite horizontal and vertical Sync and

Blank signals available

n Complete control of pulse width via register

programming

n All inputs are TTL compatible

These devices make no assumptions concerning the system

architecture. Line rate and field/frame rate are all a function

of the values programmed into the data registers, the status

n 8 mA drive on all outputs

n Default RS170/NTSC values mask programmed into

registers

n 4 KV minimum ESD immunity

n ’ACT715-R/LM1882-R is mask programmed to default to

a Clock Enable state for easier start-up into

14.31818 MHz RS170 timing

The ’ACT715/LM1882 is mask programmed to default to a

Clock Disable state. Bit 10 of the Status Register, Register 0,

defaults to a logic “0”. This facilitates (re)programming be-

fore operation.

The ’ACT715-R/LM1882-R is the same as the ’ACT715/

LM1882 in all respects except that the ’ACT715-R/

Connection Diagrams

Pin Assignment for

DIP and SOIC

Pin Assignment

for LCC

DS100232-1

DS100232-2

Order Number LM1882CN or LM1882CM

For Default RS-170, Order Number

LM1882-RCN or LM1882-RCM

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

FACT is a trademark of Fairchild Semiconductor Corporation.

DS100232

www.national.com

12 3 4 5 6 7...16

下载PDF

与54ACT715相关器件

型号	品牌	描述	获取价格	数据表
54ACT715D	TI	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20	获取价格
54ACT715DM	TI	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20	获取价格
54ACT715DMQB	NSC	IC SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20, Consumer IC:Other	获取价格
54ACT715DMQB	TI	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20	获取价格
54ACT715L	TI	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20	获取价格
54ACT715LMQB	NSC	IC SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20, Consumer IC:Other	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

54ACT715

54ACT715 技术参数

54ACT715 数据手册

与54ACT715相关器件

与54ACT715相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

54ACT715

54ACT715 技术参数

54ACT715 数据手册

与54ACT715相关器件

与54ACT715相关文章

您还可以找

您在本页遇到什么问题？