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54ACT112 PDF预览

54ACT112

更新时间: 2024-02-10 18:19:08
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
7页 140K
描述
Dual JK Negative Edge-Triggered Flip-Flop

54ACT112 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.73
Base Number Matches:1

54ACT112 数据手册

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September 1998  
54ACT112  
Dual JK Negative Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
General Description  
LOW input to SD sets Q to HIGH level  
The ’ACT112 contains two independent, high-speed JK  
flip-flops with Direct Set and Clear inputs. Synchronous state  
changes are initiated by the falling edge of the clock. Trigger-  
ing occurs at a voltage level of the clock and is not directly  
related to the transition time. The J and K inputs can change  
when the clock is in either state without affecting the flip-flop,  
provided that they are in the desired state during the recom-  
mended setup and hold times relative to the falling edge of  
the clock. A LOW signal on SD or CD prevents clocking and  
forces Q or Q HIGH, respectively. Simultaneous LOW sig-  
nals on SD and CD force both Q and Q HIGH.  
LOW input to CD sets Q to LOW level  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes both Q and Q  
HIGH  
Features  
n ’ACT112 has TTL-compatible inputs  
n Outputs source/sink 24 mA  
n Standard Microcircuit Drawing (SMD) 5962-8995001  
Connection Diagram  
Pin Descriptions  
Pin Names  
J1, J2, K1, K2  
CP1, CP2  
Description  
Pin Assigment for  
DIP and Flatpack  
Data Inputs  
Clock Pulse Inputs  
(Active Falling Edge)  
CD1, CD2  
Direct Clear Inputs (Active LOW)  
Direct Set Inputs (Active LOW)  
Outputs  
S
D1, SD2  
Q1, Q2, Q1, Q2  
DS100976-3  
Pin Assigment  
for LCC  
DS100976-5  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100976  
www.national.com  

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