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54AC273D PDF预览

54AC273D

更新时间: 2024-01-14 22:29:16
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 161K
描述
Octal D Flip-Flop

54AC273D 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.56
系列:ACJESD-30 代码:R-GDSO-G20
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):16 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:2.59 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
最小 fmax:95 MHzBase Number Matches:1

54AC273D 数据手册

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July 1998  
54AC273  
Octal D Flip-Flop  
General Description  
Features  
n Ideal buffer for microprocessor or memory  
n Eight edge-triggered D flip-flops  
n Buffered common clock  
The ’273 has eight edge-triggered D-type flip-flops with indi-  
vidual D inputs and Q outputs. The common buffered Clock  
(CP) and Master Reset (MR) input load and reset (clear) all  
flip-flops simultaneously.  
n Buffered, asynchronous master reset  
n See ’377 for clock enable version  
n See ’373 for transparent latch version  
n See ’374 for TRI-STATE® version  
n Outputs source/sink 24 mA  
n ’ACT has TTL-compatible inputs  
n Standard Military Drawing (SMD)  
— ’AC273: 5962-87756  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The de-  
vice is useful for applications where the true output only is re-  
quired and the Clock and Master Reset are common to all  
storage elements.  
Logic Symbols  
IEEE/IEC  
DS100288-1  
DS100288-2  
Pin Names  
Description  
D0–D7  
MR  
Data Inputs  
Master Reset  
CP  
Clock Pulse Input  
Data Outputs  
Q0–Q7  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT is a trademark of National Semiconductor Corporation.  
1
© 1998 National Semiconductor Corporation  
DS100288  
www.national.com  
PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof  
1

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