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54ABT652J-QML PDF预览

54ABT652J-QML

更新时间: 2024-01-04 10:24:58
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器触发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
17页 363K
描述
Octal Transceivers and Registers with TRI-STATE Outputs

54ABT652J-QML 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL24,.4Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ABT
JESD-30 代码:R-GDFP-F24JESD-609代码:e0
长度:15.4305 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL24,.4
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):30 mAProp。Delay @ Nom-Sup:6.7 ns
传播延迟(tpd):8.4 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.286 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE

54ABT652J-QML 数据手册

 浏览型号54ABT652J-QML的Datasheet PDF文件第2页浏览型号54ABT652J-QML的Datasheet PDF文件第3页浏览型号54ABT652J-QML的Datasheet PDF文件第4页浏览型号54ABT652J-QML的Datasheet PDF文件第5页浏览型号54ABT652J-QML的Datasheet PDF文件第6页浏览型号54ABT652J-QML的Datasheet PDF文件第7页 
August 1998  
54ABT652  
Octal Transceivers and Registers with TRI-STATE®  
Outputs  
n Multiplexed real-time and stored data  
n A and B output sink capability of 48 mA, source  
capability of 24 mA  
n Guaranteed latchup protection  
n High impedance glitch free bus loading during entire  
power up and power down cycle  
General Description  
The ’ABT652 consists of bus transceiver circuits with D-type  
flip-flops, and control circuitry arranged for multiplexed trans-  
mission of data directly from the input bus or from the inter-  
nal registers. Data on the A or B bus will be clocked into the  
registers as the appropriate clock pin goes to HIGH logic  
level. Output Enable pins (OEAB, OEBA) are provided to  
control the transceiver function.  
n Nondestructive hot insertion capability  
n Standard Microcircuit Drawing (SMD) 5962-9324201  
Features  
n Independent registers for A and B buses  
Ordering Code:  
Commercial  
Package  
Number  
J24A  
Package Description  
54ABT652J-QML  
24-Lead Ceramic Dual-in-line  
24-Lead Cerpack  
54ABT652W-QML  
54ABT652E-QML  
W24C  
E28A  
28-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagram  
Pin Assignment for  
DIP and Flatpack  
DS100220-1  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100220  
www.national.com  

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