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54ABT373CDMQB PDF预览

54ABT373CDMQB

更新时间: 2024-02-15 14:11:01
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
16页 331K
描述
Octal Transparent Latch with TRI-STATE Outputs

54ABT373CDMQB 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:DFP, FL20,.3Reach Compliance Code:unknown
风险等级:5.81JESD-30 代码:R-XDFP-F20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.048 A
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:CERAMIC封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
Prop。Delay @ Nom-Sup:7 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B子类别:FF/Latches
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

54ABT373CDMQB 数据手册

 浏览型号54ABT373CDMQB的Datasheet PDF文件第2页浏览型号54ABT373CDMQB的Datasheet PDF文件第3页浏览型号54ABT373CDMQB的Datasheet PDF文件第4页浏览型号54ABT373CDMQB的Datasheet PDF文件第5页浏览型号54ABT373CDMQB的Datasheet PDF文件第6页浏览型号54ABT373CDMQB的Datasheet PDF文件第7页 
September 1995  
54ABT/74ABT373  
Octal Transparent Latch with TRI-STATE Outputs  
É
Guaranteed output skew  
Y
General Description  
The ’ABT373 consists of eight latches with TRI-STATE out-  
Y
Guaranteed multiple output switching specifications  
Y
Output switching specified for both 50 pF and 250 pF  
puts for bus organized system applications. The flip-flops  
loads  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup  
times is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH the bus output is in  
the high impedance state.  
Y
Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
Y
Guaranteed latchup protection  
Y
High impedance glitch free bus loading during entire  
power up and power down  
Y
Y
Nondestructive hot insertion capability  
Features  
Y
Standard Military Drawing (SMD) 5962-9321801  
TRI-STATE outputs for bus interfacing  
Y
Output sink capability of 64 mA, source capability of  
32 mA  
Package  
Commercial  
Military  
Package Description  
Number  
M20B  
M20D  
N20B  
74ABT373CSC (Note 1)  
74ABT373CSJ (Note 1)  
74ABT373CPC  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54ABT373J/883  
J20A  
20-Lead Ceramic Dual-In-Line  
74ABT373CMSA (Note 1)  
MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II  
54ABT373W/883 W20A  
54ABT373E/883 E20A  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
74ABT373CMTC (Notes 1, 2)  
MTC20 20-Lead Molded Thin Shrink Small Outline, JEDEC  
e
Note 1: Devices also available in 13 reel. Use suffix  
×
Note 2: Contact factory for package availability.  
SCX, SJX, MSAX, and MTCX.  
Connection Diagrams  
Pin Assignment  
for DIP, SOIC, SSOP and Flatpak  
Pin Assignment  
for LCC  
Pin Names  
Description  
Data Inputs  
D D  
0
7
LE  
Latch Enable Input  
(Active HIGH)  
OE  
Output Enable Input  
(Active LOW)  
O O  
0
TRI-STATE Latch  
Outputs  
7
TL/F/11547–2  
TL/F/11547–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11547  
RRD-B30M115/Printed in U. S. A.  

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