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54ABT16646 PDF预览

54ABT16646

更新时间: 2024-02-26 05:54:39
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
8页 158K
描述
16-Bit Transceivers and Registers with TRI-STATE Outputs

54ABT16646 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:CERAMIC, FP-56Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
其他特性:WITH DIRECTION CONTROL控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ABT
JESD-30 代码:R-GDFP-F56JESD-609代码:e0
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.048 A
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL56,.4,25封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):7.7 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:2.54 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:0.64 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:9.65 mm
Base Number Matches:1

54ABT16646 数据手册

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July 1998  
54ABT16646  
16-Bit Transceivers and Registers with TRI-STATE®  
Outputs  
General Description  
Features  
n Independent registers for A and B buses  
n Multiplexed real-time and stored data  
The ’ABT16646 consists of bus transceiver circuits with  
TRI-STATE, D-type flip-flops, and control circuitry arranged  
for multiplexed transmission of data directly from the input  
bus or from the internal registers. Data on the A or B bus will  
be clocked into the registers as the appropriate clock pin  
goes to a high logic level. Control OE and direction pins are  
provided to control the transceiver function. In the trans-  
ceiver mode, data present at the high impedance port may  
be stored in either the A or the B register or in both. The  
select controls can multiplex stored and real-time (transpar-  
ent mode) data. The direction control determines which bus  
will receive data when the enable control OE is Active LOW.  
In the isolation mode (control OE HIGH), A data may be  
stored in the B register and/or B data may be stored in the A  
register.  
n A and B output sink capability of 48 mA, source  
capability of 24 mA  
n Guaranteed latchup protection  
n High impedance glitch free bus loading during entire  
power up and power down cycle  
n Nondestructive hot insertion capability  
n Standard Microcircuit Drawing (SMD) 5962-9450202  
Ordering Code  
Military  
Package  
Number  
WA56A  
Package Description  
54ABT16646W-QML  
56-Lead Cerpack  
Logic Symbol  
Pin Names  
A0–A15  
Description  
Data Register A Inputs/  
TRI-STATE Outputs  
Data Register B Inputs/  
TRI-STATE Outputs  
Clock Pulse Inputs  
Select Inputs  
B0–B15  
CPABn, CPBAn  
SABn, SBAn  
OEn  
Output Enable Input  
Direction Control Input  
DIR  
DS100226-1  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2004 National Semiconductor Corporation  
DS100226  
www.national.com  

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